Table 5-1 — Physical Device Identifier Values [A0h Byte 0]

Table 5-2 — Physical Device Extended Identifier Values [A0h Byte 1]

00h unspecified/non-MOD_DEF · 01h-03h,05h-07h MOD_DEF 1/2/3/5/6/7 · 04h = 2-wire interface ID only (standard SFP) · 08-FFh Reserved.

Table 5-3 — Transceiver Compliance Codes [A0h Bytes 3-10, 36, 62] — full bit map

Bytes 3-6: 10GE / InfiniBand / ESCON / SONET compliance bits. Byte 7: Ethernet (incl. BASE-PX, BASE-BX10, 100BASE-FX, 100BASE-LX/LX10, 1000BASE-T/CX/LX/SX). Byte 8: Fibre Channel link length + SFP+ Cable Technology (bit3 Active Cable, bit2 Passive Cable). Byte 9: FC transmission media (Twin-Ax, Twisted Pair, Coax, MMF 62.5/50um, SM). Byte 10: FC speed (100-1200 MBytes/s) + bit1 → "see byte 62". Byte 62 bit0: 64GFC.
(Full bit-by-bit table extracted in sff8472_full.txt lines ~1150-1200 if per-bit reconstruction is needed later.)

Table 8-3 — Option Values [A0h Byte 64-65] — key bits

• 64.6/64.5: High Power Level Declaration (Power Level 3/4)
• 64.4: Paging implemented
• 64.3: Retimer or CDR indicator (module has internal retimer/CDR)
• 64.2: Cooled Transceiver
• 64.1: Power Level 2
• 64.0: Linear Receiver Output
• 65.7: Receiver Decision Threshold (RDT) implemented
• 65.6: Tunable transmitter (SFF-8690)
• 65.5: RATE_SELECT implemented
• 65.4: TX_DISABLE implemented
• 65.3: TX_FAULT implemented
• 65.2: LOS implemented, inverted (non-standard, deprecated)
• 65.1: LOS implemented, standard (SFF-8419)
• 65.0: Paging discovery flag (additional pages exist)

Table 8-5 — Diagnostic Monitoring Type [A0h Byte 92]

7 Reserved(must be 0) · 6 Digital diagnostic monitoring implemented · 5 Internally calibrated · 4 Externally calibrated · 3 Rx power type (0=OMA,1=avg) · 2 Address change required · 1 = Remote Performance Monitoring Registers (Section 12) — new since 12.x · 0 Reserved.

Table 8-8 — SFF-8472 Compliance [A0h Byte 94] — ★ direct comparison to old file★

Gap: old file's table stops representation at 03h(Rev10.2); official table now runs to 0Ah(Rev12.5) — 7 newer compliance values (04h-0Ah) are absent from the old sheet.

Table 9-5 — Alarm and Warning Thresholds [A2h 0-55], 2-byte MSB-first pairs, in order:

Temp High/Low Alarm, Temp High/Low Warning, Voltage High/Low Alarm, Voltage High/Low Warning, Bias High/Low Alarm, Bias High/Low Warning, TX Power High/Low Alarm, TX Power High/Low Warning, RX Power High/Low Alarm, RX Power High/Low Warning [bytes 0-39], then Optional Laser Temp High/Low Alarm/Warning, Optional TEC Current High/Low Alarm/Warning [bytes 40-55].

Table 9-6 — External Calibration Constants [A2h 56-91] (used when A0h.92.4=1)

Rx_PWR(4)..Rx_PWR(0) [56-75, 4 bytes each, IEEE-754 float] → Tx_I(Slope) [76-77] → Tx_I(Offset) [78-79] → Tx_PWR(Slope) [80-81] → Tx_PWR(Offset) [82-83] → T(Slope) [84-85] → T(Offset) [86-87] → V(Slope) [88-89] → V(Offset) [90-91].

Table 9-16 — A/D Values and Status Bits [A2h 96-110]

96-97 Temperature (MSB/LSB) · 98-99 Vcc · 100-101 TX Bias · 102-103 TX Power · 104-105 RX Power · 106-107 Optional Laser Temp/Wavelength · 108-109 Optional TEC current.
Byte 110 status bits: 7 TX Disable State · 6 Soft TX Disable Select · 5 RS(1) State · 4 Rate_Select State [RS(0)] · 3 Soft Rate_Select Select · 2 TX Fault State · 1 Rx_LOS State · 0 Data_Not_Ready.

Table 10-1 — Extended Module Control/Status [A2h 118-119]

118: bit4 Adaptive Input EQ Fail Flag · bit3 Soft RS(1) Select · bit2 Power Level 4 Enable · bit1 Power Level Operation State · bit0 Power Level Select.
119: bit4 PAM4 Mode Tx Configured · bit3 PAM4 Mode Rx Configured · bit2 64GFC Mode · bit1 Optional Tx CDR unlocked · bit0 Optional Rx CDR unlocked. (64GFC/PAM4 bits are relatively recent additions not in earlier SFF-8472 revisions — check old file for their presence.)

Table 10-3 — Optional Page Select [A2h 127]

Defines pages 00h-03h and 20h-27h; 04h-1Fh/28h-7Fh reserved; 80h-FFh vendor. Page defaults to 00h at power-up.

These two full pages did not exist as populated tables in the old 通用A2低位/通用A2 Page0 sheets and must be added as new sheets/sections.

§12 — A2h Page 02h: Tunability, RDT, and Remote Performance Monitoring (Table 12-1)

Table 12-2 (byte 129, Feature Advertisement): bit2 RPM supported · bit1 RDTcurrval readable · bit0 RDTmode (0=legacy≤12.4 behavior, 1=new 12.5 behavior).

Table 12-5 — Remote Performance Monitoring register summary:
| A2h | Function |
|---|---|
| 129 | RPM Feature Advertisement |
| 174-175 | COR latched alarms (Table 12-6: L-RxUserData, L-RxUserChanged, L-TxUserSending, L-TxUserDataOvrrun, L-GlobalRxError, L-MsgError, L-TomError, L-FrameUnlock) |
| 192-197 | Clock Status/Debug registers |
| 198-207 | Frame error counters (BER/FER calc) |
| 208-210 | Tx Remote Cmd (remote memory map write) |
| 211 | Tx RPM Modulation Index / disable |
| 212-219 | Control registers |
| 220-239 | Reserved |
| 240-247 | User Remote TX Data (host write, write to byte247 triggers send) |
| 248-255 | User Remote RX Data (read only) |

RPM signaling: 5 kbps ±50,000ppm on-media low-speed channel per ITU-T G.698.4 framing (11-bit TOM + 5-bit CRC, 24-bit MSG + 8-bit CRC, 48-bit frame), extended with 5 new TOM codes per "MOPA Remote Monitoring Specification". Remote transceiver's entire memory map is exposed locally at Pages 20h-27h.

§13 — A2h Page 03h: High Accuracy Timing Calibration (Optical: Table 13-1 / Loopback: Table 13-2)

Format ID at bytes 128-129 selects layout: CA1Bh='CALB' (Optical) or 100Bh='LOOB' (Loopback).

Optical Module format (Table 13-1):
128-129 Format ID · 130-149 Common Header · 150 Nb_Lanes(=1 for SFF-8472) · 151 Op_Mode_Id(=0) · 152-166 Rx_Pwr_Dly(0-4) curve coefficients · 167-170 T_Detune_Offset/Slope · 171-174 Delta_Rx_Max · 175-178 Delta_Tx_Max · 179-182 Avg_Rx_Lane · 183-186 Avg_Tx_Lane · 187-254 Reserved(00h) · 255 CC_CALIB.

Loopback Module format (Table 13-2):
128-129 Format ID · 130-149 Common Header · 150-153 Calibration Inaccuracy · 155-158 Tx_to_Rx Delay · 160-163 Tx_to_Mon Delay · 165-168 Rx_to_Mon Delay · 255 CC_CALIB.

Purpose: IEEE 1588 / IEEE 802.3cx PTP timestamp delay compensation between electrical and optical reference planes.

Table 4-1 — Identifier Values [A0h Byte 0, full SFF-8024 master list]

Includes everything from 00h Unknown through modern form factors: 0Dh QSFP+/SFF-8636, 11h QSFP28/SFF-8636, 18h QSFP-DD, 19h OSFP, 1Ah SFP-DD, 1Bh DSFP, 1Eh QSFP+ w/ CMIS, 1Fh SFP-DD w/ CMIS, 20h SFP+ w/ CMIS, 21h OSFP-XD w/ CMIS, 22h OIF-ELSFP w/ CMIS, 23h/24h/25h CDFP x4/x8/x16 PCIe w/ CMIS, 26h XPO — this whole CMIS-form-factor block (1Eh-26h) is new vs older SFF-8024 editions and worth cross-checking against the old files' Identifier lookup lists.

Table 4-2 — Encoding Values

00h Unspecified · 01h 8B/10B · 02h 4B/5B · 03h NRZ · 04h Manchester(8472)/06h(8636-family) · 05h SONET Scrambled(8472)/04h(8636) · 06h 64B/66B(8472)/05h(8636) · 07h 256B/257B · 08h PAM4. ⚠ Note the 8472 vs 8436/8636 code values diverge for Manchester/SONET-Scrambled/64B66B — old files must use the correct column per protocol.

Table 4-3 — Connector Types [full list]

00h Unknown · 01h SC · 02h/03h FC copper · 04h BNC/TNC · 05h FC coax · 06h Fiber Jack · 07h LC · 08h MT-RJ · 09h MU · 0Ah SG · 0Bh Optical Pigtail · 0Ch MPO1x12 · 0Dh MPO2x16 · 20h HSSDC II · 21h Copper pigtail · 22h RJ45 · 23h No separable connector · 24h MXC2x16 · 25h CS optical · 26h SN(mini CS) optical · 27h MPO2x12 · 28h MPO1x16 (25h-28h are newer additions) · 80h-FFh Vendor specific.

Table 4-4 — Extended Specification Compliance Codes [full 00h-81h list extracted]

Covers legacy 100G codes (01h-1Fh: SR4/LR4/ER4/CWDM4/PSM4/CR4 etc.) through modern additions: 25h 100GBASE-DR, 26h/27h 100G-FR/LR (100GBASE-FR1/LR1), 28h/3Ah 100GBASE-SR1/VR1, 29h/36h 100/200/400GBASE-SR/VR (Clause167), 2Ah 100GBASE-FR1 or 400GBASE-DR4-2, 30h-33h AOC/ACC BER-graded codes, 3Fh 100/200/400GBASE-CR (Clause162), 40h-4Ah 50/100/200GBASE family (CR/SR/FR/DR/LR), 47h-4Ch 400GBASE-DR4/FR4/LR4-6/ZR(obsolete), 7Fh 256GFC-SW4, 80h/81h 64GFC/128GFC. Full table transcribed with all codes and footnotes in the section above — recommend pasting verbatim into new lookup sheet since it's large (85+ rows, matches old file's 85-row "Extended Compliance Code" sheet size almost exactly — good candidate for direct 1:1 replacement).

• Table 5-4 (SONET Reach Specifier Bits), 5-5 (examples), 5-6 (Rate Identifier), 9-11 through 9-15 (Additional Enhanced Features, bit-level), 9-17 (Alarm/Warning Flag Bits, full bit list), 9-18/9-19 (Tx EQ / Rx Emphasis control values), 10-2 (Retimer/CDR Rate Select Logic), 11-1/11-2 (User EEPROM / Vendor control) — these exist in the source PDF and were spot-checked but not fully transcribed here due to time budget; pull from sff8472_full.txt (grep for the table number) before finalizing the workbook.
• SFF-8024 Table 4-5 onward (Host Electrical Interface IDs, MMF/SMF/Copper/BaseT media interface IDs) were not extracted — CMIS fork's SFF-8024 needs likely overlap here; check for duplication before re-extracting.
• Table 5-3 per-bit reconstruction (Ethernet/FC/SONET compliance bit grid) was summarized rather than transcribed cell-by-cell — needed if the "綜合版" workbook keeps the old file's per-bit row format for A0h bytes 3-10.

Extracted verbatim from the PDF's own Revision History (pages 3-7):

Rev 2.10 → Rev 2.10a (Sept 2019)

• Cosmetic only: removed "draft" from cover page.

Rev 2.10a → Rev 2.11 (January 3, 2023)

• Replaced "master/slave" terminology with "controller/target" throughout.
• Added Transceiver Subtype code and Fiber Face type code at Page 00h, Byte 117 (moved Byte 117 out of Reserved into the Free Side Device Properties group — Table 6-1 / Table 5-3).
• Re-labeled the old "Figure 6-1" memory-map diagram as Table 6-1, renumbering all subsequent tables (this is why the old file's table numbers/labels no longer line up 1:1 with the current spec — every table from the old "Table 6-3 Revision Compliance" era is now offset).
• "Bit rate" reworded to "signaling rate"/"rate" throughout (PAM4 clarity), no register impact.

Rev 2.11 → Rev 2.12 (April 29, 2026 — current)

• Removed reserved bytes for lanes 2-4, restructuring the register layout to accommodate a future 8-lane variant. (Any old-file rows describing those former per-lane-2/3/4 reserved bytes need re-checking against the new Table 6-1/6-2 layout — flagged below.)
• Table 6-4 (Revision Compliance) gained two new rows: 09h = SFF-8636 Rev 2.11, 0Ah = SFF-8636 Rev 2.12. The old file's lookup only goes to 08h.
• New §7 "Optional High Accuracy Timing" registers added on Page 22h, extending the single-lane High Accuracy Timing feature that SFF-8472 already has to four lanes. This is an entirely new page with no equivalent anywhere in the old file (which only covers Lower Page, Upper Page 00h, and Upper Page 03h).
• Formatting-only: inclusive byte-range notation changed from N(1,4) to N(1-4); new references alphabetized.

Tables that live in SFF-8024, not SFF-8636 itself (confirmed from Revision History, do not fabricate content here)

• Module/Transceiver Identifier Values — moved to SFF-8024 per Rev 1.3/1.7.
• Connector Type codes — moved to SFF-8024 per Rev 2.2.
• Encoding Values — returned to SFF-8024 per Rev 2.2 (Rev 1.3 first pointed there).
• Extended Specification Compliance Codes (the "Extended" bit within Table 6-17, byte 131 bit 7 / byte 138 bit 1) — maintained in SFF-8024 Transceiver Management section, per Rev 1.7 and confirmed again in the Table 6-17 text itself (below).
• The base Specification Compliance Codes (bytes 131-138, non-extended bits) ARE reproduced directly in SFF-8636 body — see Table 6-17 below.
• Transmitter Technology (byte 147 bits 7-4) IS reproduced directly in SFF-8636 body — see Table 6-20 below. (Not SFF-8024-only, unlike the four items above.)

Action needed for the consolidated file: the four SFF-8024-only lookup sheets in the old workbook (Module Identifier Values, Connector Types, Extended Compliance Code, Encoding Values) must be sourced from SFF-8024 Rev 4.14, not from SFF-8636 — that extraction is tracked separately.

(PDF p.29)

Table 6-1  Common Memory Map 

From To Content No. of 
bytes 
Type 
2-Wire Serial Address 1010000x 
Lower Page 00h 
0 2 ID and Status 3 Read-Only 
3 21 Interrupt Flags (Clear on read) 19 Read-Only 
22 33 Free Side Device Monitors 12 Read-Only 
34 81 Channel Monitors 48 Read-Only 
82 85 Reserved 4 Read-Only 
86 99 Control 14 Read/Write 
100 106 Free Side Interrupt Masks 7 Read/Write 
107 110 Free Side Device Properties 4 Read-Only 
111 112 Assigned to PCI Express 2 Read/Write 
113 117 Free Side Device Properties 5 Read-Only 
118 118 Reserved 1 Read/Write 
119 122 Optional Password Change 4 Write-Only 
123 126 Optional Password Entry 4 Write-Only 
127 127 Page Select Byte 1 Read/Write 
Upper Page 00h 
128 128 Identifier 1 Read-Only 
129 191 Base ID Fields 63 Read-Only 
192 223 Extended ID 32 Read-Only 
224 255 Vendor Specific ID 32 Read-Only 
Page 01h  (Optional) 
128 255 Reserved (previously for SFF-8079 support) 128 Read-Only 
Page 02h  (Optional) 
128 255 User EEPROM Data 128 Read/Write 
Page 03h (Optional) 
128 175 Free Side Device Thresholds 48 Read-Only 
176 223 Channel Thresholds 48 Read-Only 
224 229 Tx EQ, Rx Output and TC Support 6 Read-Only 
230 241 Channel Controls 12 Read/Write 
242 251 Channel Monitor Masks 10 Read/Write 
252 255 Reserved 4 Read/Write 
Pages 04h-1Fh  (Optional) 
128 255 Vendor Specific 128 Read/Write 
Pages 20h-21h  (Optional) 
128 255 PAM-4 and WDM Features 128 Read/Write 
Pages 22h  (Optional) 
128 255 High Accuracy Timing 128 Read/Write 
Pages 23h-7Fh  (Optional) 
128 255 Reserved 128 Read/Write 
Pages 80h-FFh  (Optional) 
128 255 Vendor Specific 128 Read/Write 


Note: Unless specifically stated otherwise, all informative ID fields must contain accurate data. Using a value of 0 
to indicate a field is unspecified (as is common in the SFP definition) is not permitted. Reserved memory locations 
are to be filled with logic z eros in all bit locations for reserved bytes, and in reserved bit locations for partially 
specified byte locations. 

6.1.1 Required Versus Optional Functionality 
The memory map tables contained within this section include columns for passive cables (PC), active cables (AC), 
active optical cables (AO) and separable modules (SM). Depending on the free side device type, some common 
memory map parameters are optional. In each column, one of three options is specified: required (R), optional (O) 
or conditional upon another parameter which is optional (C).  Entries with a dash (-) indicate that whether the byte 
or bit is required is not relevant. 




6.2 Lower Page 00h 
Lower Page 00h is used to access a variety of measurement, diagnostic and control functions. In addition, a 
mechanism to select upper memory map pages is provided. This portion of the address space is always directly 
addressable and thus is chosen for monitoring and control functions that may need to be repeatedly accessed. 

(PDF p.31)

Table 6-2  Lower Page 00h Memory Map 
Byte Description Type PC AC AO SM 
0 Identifier (See SFF-8024 Transceiver Management) Read-Only R R R R 
1-2 Status Read-Only See Table 6-3 
3-21 Interrupt Flags Read-Only See Table 6-5, Table 6-6 
and Table 6-7 
22-33 Free Side Device Monitors Read-Only See Table 6-8 
34-81 Channel Monitors Read-Only See Table 6-9 
82-85 Reserved Read-Only - 
86-99 Control Read/Write See Table 6-10 
100-106 Free Side Device and Channel Masks Read/Write See Table 6-13 
107-110 Free Side Device Properties Read-Only See Table 6-14 
111-112 Assigned for use by PCI Express Read/Write See Table 6-14 
113-117 Free Side Device Properties Read-Only See Table 6-14 
118 Reserved Read/Write - 
119-122 Password Change Entry Area Write-Only O O O O 
123-126 Password Entry Area Write-Only O O O O 
127 Page Select Byte Read/Write R R R R 

6.2.1 Identifier 
Page 00h Byte 0 and Page 00h Byte 128 shall contain the same parameter values. See 6.3.1 for parameter 
description. See document SFF-8024 Transceiver Management section for the definition of valid values. 

6.2.2 Status Indicators (Page 00h, Bytes 1-2) 

(PDF p.31)

Table 6-3  Status Indicators (Page 00h Bytes 1-2) 
Byte 

Bit Name Description PC AC AO SM 
1 All Revision 
Compliance  
See Table 6-4. R R R R 
2 7-4 Reserved Module State Code – reserved for microQSFP MSA. - - - - 
3 Reserved  - - - - 
2 Flat_mem Upper memory flat or paged.  
Bit 2 = 1b: Flat memory (lower and upper pages 
00h only), 
Bit 2 = 0b: Paging (at least upper page 03h 
implemented), 
See Page 00h, Byte 195 for additional advertising. 
R R R R 
1 IntL Digital state of the IntL Interrupt output pin. 1 = 
IntL not asserted, 0 = IntL asserted.  Default = 1. 
R R R R 
0 Data_Not_Ready Indicates free-side does not yet have valid monitor 
data. The bit remains high until valid data can be 
read at which time the bit goes low. 
R R R R 

The Data_Not_Ready bit shall be asserted high during free -side device reset, power up reset and prior to a valid 
suite of monitor readings. Once all monitor readings are valid, the bit is set low until the device is powered down 


or reset. Upon completion of power-up reset, the free -side device shall assert the IntL output signal and bit (if 
supported) low while de -asserting the Data_Not_Ready bit low. The IntL bit will remain asserted until a read is 
performed of the Data_Not_Ready bit (Byte 2). 

(PDF p.32)

Table 6-4  Revision Compliance (Page 00h Byte 1) 
Value Memory Map Version 
00h Revision not specified. Do not use for SFF-8636 rev 2.5 or higher. 
01h SFF-8436 Rev 4.8 or earlier 
02h Includes functionality described in revision 4.8 or earlier of SFF-8436, except that 
this byte and Bytes 186-189 are as defined in this document 
03h SFF-8636 Rev 1.3 or earlier 
04h SFF-8636 Rev 1.4 
05h SFF-8636 Rev 1.5 
06h SFF-8636 Rev 2.0 
07h SFF-8636 Rev 2.5, 2.6 and 2.7 
08h SFF-8636 Rev 2.8, 2.9 and 2.10 
09h SFF-8636 Rev 2.11 
0Ah SFF-8636 Rev 2.12 
0B-FFh Reserved 

6.2.3 Interrupt Flags (Page 00h, Bytes 3-21) 
Bytes 3-21 consist of interrupt flags for LOS, Tx Fault, warnings and alarms. The non-asserted state shall be 0b. If 
an interrupt flag condition is true, the free side shall assert the corresponding flag bit to 1b. The flag bit shall remain 
set until the fixed-side performs a read operation of the bit or the free side is reset. Flag bits cleared while underlying 
interrupt condition remains true may be immediately set again by the free side device. During this process, the IntL 
output signal may be re-asserted if the associated mask bit is not set. These flags may be masked. 

(PDF p.33)

Table 6-5  Channel Status Interrupt Flags (Page 00h Bytes 3-5) 
Byte Bit Name Description PC AC AO SM 
3 7 L-Tx4 LOS Latched Tx4 LOS indicator O O O O 
6 L-Tx3 LOS Latched Tx3 LOS indicator O O O O 
5 L-Tx2 LOS Latched Tx2 LOS indicator O O O O 
4 L-Tx1 LOS Latched Tx1 LOS indicator O O O O 
3 L-Rx4 LOS Latched Rx4 LOS indicator O O O O 
2 L-Rx3 LOS Latched Rx3 LOS indicator O O O O 
1 L-Rx2 LOS Latched Rx2 LOS indicator O O O O 
0 L-Rx1 LOS Latched Rx1 LOS indicator O O O O 
4 7 L-Tx4 Adapt EQ Fault Latched Tx4 input Adaptive EQ fault indicator O O O O 
6 L-Tx3 Adapt EQ Fault Latched Tx3 input Adaptive EQ fault indicator O O O O 
5 L-Tx2 Adapt EQ Fault Latched Tx2 input Adaptive EQ fault indicator O O O O 
4 L-Tx1 Adapt EQ Fault Latched Tx1 input Adaptive EQ fault indicator O O O O 
3 L-Tx4 Fault Latched Tx4 Transmitter/Laser fault indicator O O O R 
2 L-Tx3 Fault Latched Tx3 Transmitter/Laser fault indicator O O O R 
1 L-Tx2 Fault Latched Tx2 Transmitter/Laser fault indicator O O O R 
0 L-Tx1 Fault Latched Tx1 Transmitter/Laser fault indicator O O O R 
5 7 L-Tx4 LOL Latched Tx4 CDR LOL indicator O O O O 
6 L-Tx3 LOL Latched Tx3 CDR LOL indicator O O O O 
5 L-Tx2 LOL Latched Tx2 CDR LOL indicator O O O O 
4 L-Tx1 LOL Latched Tx1 CDR LOL indicator O O O O 
3 L-Rx4 LOL Latched Rx4 CDR LOL indicator O O O O 
2 L-Rx3 LOL Latched Rx3 CDR LOL indicator O O O O 
1 L-Rx2 LOL Latched Rx2 CDR LOL indicator O O O O 
0 L-Rx1 LOL Latched Rx1 CDR LOL indicator O O O O 

(PDF p.33)

Table 6-6  Free Side Monitor Interrupt Flags (Page 00h Bytes 6-8) 
Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
6 7 L-Temp High Alarm Latched high-temperature alarm O O O R 
6 L-Temp Low Alarm Latched low-temperature alarm O O O O 
5 L-Temp High Warning Latched high-temperature warning O O O O 
4 L-Temp Low Warning Latched low-temperature warning O O O O 
3-2 Reserved  - - - - 
1 TC readiness flag Asserted (one) after TC has stabilized. Returns 
to zero when read. Does not reassert until the 
module is reset or re -enters high power mode 
from low power mode. See Table 6-25 for the 
TC Readiness Implemented bit. 
O O O O 
0 Initialization complete 
flag 
Asserted (one) after initialization and/or reset 
has completed. Returns to zero when read. 
Does not reassert unless reset. See Table 6-25 
for the Initialization Complete Implemented 
bit. 
O O O O 
7 7 L-Vcc High Alarm Latched high supply voltage alarm O O O O 
6 L-Vcc Low Alarm Latched low supply voltage alarm O O O O 
5 L-Vcc High Warning Latched high supply voltage warning O O O O 
4 L-Vcc Low Warning Latched low supply voltage warning O O O O 
3-0 Reserved  - - - - 
8 All Vendor Specific  - - - - 

(PDF p.34)

Table 6-7  Channel Monitor Interrupt Flags (Page 00h Bytes 9-21) 
Byte Bit Name Description PC AC AO SM 
9 7 L-Rx1 Power High Alarm Latched Rx1 high power alarm O O O O 
6 L-Rx1 Power Low Alarm Latched Rx1 low power alarm O O O O 
5 L-Rx1 Power High Warning Latched Rx1 high power warning O O O O 
4 L-Rx1 Power Low Warning Latched Rx1 low power warning O O O O 
3 L-Rx2 Power High Alarm Latched Rx2 high power alarm O O O O 
2 L-Rx2 Power Low Alarm Latched Rx2 low power alarm O O O O 
1 L-Rx2 Power High Warning Latched Rx2 high power warning O O O O 
0 L-Rx2 Power Low Warning Latched Rx2 low power warning O O O O 
10 7 L-Rx3 Power High Alarm Latched Rx3 high power alarm O O O O 
6 L-Rx3 Power Low Alarm Latched Rx3 low power alarm O O O O 
5 L-Rx3 Power High Warning Latched Rx3 high power warning O O O O 
4 L-Rx3 Power Low Warning Latched Rx3 low power warning O O O O 
3 L-Rx4 Power High Alarm Latched Rx4 high power alarm O O O O 
2 L-Rx4 Power low Alarm Latched Rx4 low power alarm O O O O 
1 L-Rx4 Power high Warning Latched Rx4 high power warning O O O O 
0 L-Rx4 Power low warning Latched Rx4 low power warning O O O O 
11 7 L-Tx1 Bias High Alarm Latched Tx1 high bias alarm O O O O 
6 L-Tx1 Bias Low Alarm Latched Tx1 low bias alarm O O O O 
5 L-Tx1 Bias high Warning Latched Tx1 high bias warning O O O O 
4 L-Tx1 Bias Low Warning Latched Tx1 low bias warning O O O O 
3 L-Tx2 Bias High Alarm Latched Tx2 high bias alarm O O O O 
2 L-Tx2 Bias Low Alarm Latched Tx2 low bias alarm O O O O 
1 L-Tx2 Bias High Warning Latched Tx2 high bias warning O O O O 
0 L-Tx2 Bias Low Warning Latched Tx2 low bias warning O O O O 
12 7 L-Tx3 Bias High Alarm Latched Tx3 high bias alarm O O O O 
6 L-Tx3 Bias Low Alarm Latched Tx3 low bias alarm O O O O 
5 L-Tx3 Bias High Warning Latched Tx3 high bias warning O O O O 
4 L-Tx3 Bias Low Warning Latched Tx3 low bias warning O O O O 
3 L-Tx4 Bias High Alarm Latched Tx4 high bias alarm O O O O 
2 L-Tx4 Bias Low Alarm Latched Tx4 low bias alarm O O O O 
1 L-Tx4 Bias High Warning Latched Tx4 high bias warning O O O O 
0 L-Tx4 Bias Low Warning Latched Tx4 low bias warning O O O O 
13 7 L-Tx1 Power High Alarm Latched Tx1 high power alarm O O O O 
6 L-Tx1 Power Low Alarm Latched Tx1 low power alarm O O O O 
5 L-Tx1 Power High Warning Latched Tx1 high power warning O O O O 
4 L-Tx1 Power Low Warning Latched Tx1 low power warning O O O O 
3 L-Tx2 Power High Alarm Latched Tx2 high power alarm O O O O 
2 L-Tx2 Power Low Alarm Latched Tx2 low power alarm O O O O 
1 L-Tx2 Power High Warning Latched Tx2 high power warning O O O O 
0 L-Tx2 Power Low Warning Latched Tx2 low power warning O O O O 
14 7 L-Tx3 Power High Alarm Latched Tx3 high power alarm O O O O 
6 L-Tx3 Power Low Alarm Latched Tx3 low power alarm O O O O 
5 L-Tx3 Power High Warning Latched Tx3 high power warning O O O O 
4 L-Tx3 Power Low Warning Latched Tx3 low power warning O O O O 
3 L-Tx4 Power High Alarm Latched Tx4 high power alarm O O O O 
2 L-Tx4 Power Low Alarm Latched Tx4 low power alarm O O O O 
1 L-Tx4 Power High Warning Latched Tx4 high power warning O O O O 
0 L-Tx4 Power Low Warning Latched Tx4 low power warning O O O O 
15-16 All Reserved Reserved channel monitor flags, set 4 - - - - 
17-18 All Reserved Reserved channel monitor flags, set 5 - - - - 
19-21 All Vendor Specific  - - - - 


6.2.4 Free Side Device Monitors (Page 00h, Bytes 22-33) 
Real-time monitoring for the free side device includes internal temperature and supply voltage. In addition there 
are optional monitors for the optical lanes of separable modules.  

The fixed side shall use 2 -byte reads to retrieve the 16-bit measurements to guarantee data coherency. The free 
side device shall prevent the host from acquiring partially updated multi -byte data during a 2 -byte read. Clock 
stretching provides one mechanism to delay the delivery of data until both bytes of a field are updated. The data 
format may facilitate greater resolution and range than required. Reference of the specific product specification of 
the free side device or interoperability standard is necessary to determine the measurement accuracy. 

Measurements are calibrated over vendor specified operating temperature and voltage and should be interpreted 
as defined below. Alarm and warning threshold values should be interpreted in the same manner as real-time 16-
bit data. 

(PDF p.35)

Table 6-8  Free Side Monitoring Values (Page 00h Bytes 22-33) 
Byte Bit Name Description PC AC AO SM 
22 All Temperature MSB Internally measured temperature (MSB) O O O R 
23 All Temperature LSB Internally measured temperature (LSB) O O O R 
24-25 All Reserved  - - - - 
26 All Supply Voltage MSB Internally measured supply voltage (MSB) O O O O 
27 All Supply Voltage LSB Internally measured supply voltage (LSB) O O O O 
28-29 All Reserved  - - - - 
30-33 All Vendor Specific  - - - - 

Internally measured free side device temperatures are represented as a 16 -bit signed twos complement value in 
increments of 1/256 degrees Celsius, yielding a total range of -128 ºC to +127 ºC that is considered valid between 
-40 ºC and +125 ºC. Temperature accuracy is vendor specific but must be better than +/ -3 ºC over the specified 
operating temperature and voltage. Placement of the temperature sensor is vendor specific.  

Internally measured free side device supply voltages are represented as a 16-bit unsigned integer with the voltage 
defined as the full 16-bit value (0 to 65535) with LSB equal to 100 µV, yielding a total measurement range of 0 to 
+6.55 V. Practical considerations to be defined by free side device manufacturer will tend to limit the actual bounds 
of the supply voltage measurement. Accuracy is Vendor Specific but must be better than +/ -3% of the 
manufacturer's nominal value over specified operating temperature and voltage. 

6.2.5 Channel Monitors (Page 00h, Bytes 34-81) 
Real-time channel monitoring for each transmit and receive channel includes optical input power and Tx bias 
current.  

Measurements are calibrated over vendor specified operating temperature and voltage and should be interpreted 
as defined below. Alarm and warning threshold values should be interpreted in the same manner as real-time 16-
bit data.  

(PDF p.36)

Table 6-9  Channel Monitoring Values (Page 00h Bytes 34-81) 
Byte Bit Name Description PC AC AO SM 
34 All Rx1 Power MSB Internally measured Rx1 input power O O O O 
35 All Rx1 Power LSB O O O O 
36 All Rx2 Power MSB Internally measured Rx2 input power O O O O 
37 All Rx2 Power LSB O O O O 
38 All Rx3 Power MSB Internally measured Rx3 input power O O O O 
39 All Rx3 Power LSB O O O O 
40 All Rx4 Power MSB Internally measured Rx4 input power O O O O 
41 All Rx4 Power LSB O O O O 
42 All Tx1 Bias MSB Internally measured Tx1 bias O O O O 
43 All Tx1 Bias LSB O O O O 
44 All Tx2 Bias MSB Internally measured Tx2 bias O O O O 
45 All Tx2 Bias LSB O O O O 
46 All Tx3 Bias MSB Internally measured Tx3 bias O O O O 
47 All Tx3 Bias LSB O O O O 
48 All Tx4 Bias MSB Internally measured Tx4 bias O O O O 
49 All Tx4 Bias LSB O O O O 
50 All Tx1 Power MSB Internally measured Tx1 Power O O O O 
51 All Tx1 Power LSB O O O O 
52 All Tx2 Power MSB Internally measured Tx2 Power O O O O 
53 All Tx2 Power LSB O O O O 
54 All Tx3 Power MSB Internally measured Tx3 Power O O O O 
55 All Tx3 Power LSB O O O O 
56 All Tx4 Power MSB Internally measured Tx4 Power O O O O 
57 All Tx4 Power LSB O O O O 
58-65  Reserved channel monitor set 4 - - - - 
66-73  Reserved channel monitor set 5 - - - - 
74-81  Vendor Specific - - - - 

Measured Tx bias current is represented in mA as a 16-bit unsigned integer with the current defined as the full 16-
bit value (0 to 65535) with LSB equal to 2 µA, yielding a total measurement range of 0 to 131 mA. Accuracy is 
Vendor Specific but must be better than +/ -10% of the manufacturer's nominal value over specified operating 
temperature and voltage. 

Measured Rx received optical power is represented in mW as either an average received power or OMA depending 
upon how Page 00h Byte 220 bit 3 is set. The parameter is encoded as a 16 -bit unsigned integer with the power 
defined as the full 16-bit value (0 to 65535) with LSB equal to 0.1 µW, yielding a total measurement range of 0 to 
6.5535 mW (~-40 to +8.2 dBm). Absolute accuracy is dependent upon the exact optical wavelength. For the vendor 
specified wavelength, accuracy shall be better than +/-3 dB over specified temperature and voltage. This accuracy 
shall be maintained for input power levels up to the lesser of maximum transmitted or maximum received optical 
power per the appropriate standard. It shall be maintained down to the minimum transmitted power m inus cable 
plant loss (insertion loss or passive loss) per the appropriate standard. Absolute accuracy beyond this minimum 
required received input optical power range is vendor specific. 

Measured Tx optical power is the average power represented in mW. The parameter is encoded as a 16-bit unsigned 
integer with the power defined as the full 16 -bit value (0 to 65535) with LSB equal to 0.1 µW, yielding a total 
measurement range of 0 to 6.5535 mW (~ -40 to +8.2 dBm). For the vendor specified wavelength, accuracy shall 
be better than +/-3 dB over specified temperature and voltage. 



6.2.6 Control Functions (Page 00h, Bytes 86-99) 

(PDF p.37)

Table 6-10  Control Function Bytes (Page 00h Bytes 86-99) 
Byte Bit Name Description PC AC AO SM 
86 7-4 Reserved  - - - - 
3 Tx4 Disable Read/Write bit for software disable of Tx4 * - O O R 
2 Tx3 Disable Read/Write bit for software disable of Tx3 * - O O R 
1 Tx2 Disable Read/Write bit for software disable of Tx2 * - O O R 
0 Tx1 Disable Read/Write bit for software disable of Tx1 * - O O R 
* For the case of an electrical/optical transceiver, writing '1' disables the laser of the channel  
87 7 Rx4_Rate_select Software rate select. Rx Channel 4 MSB - O O O 
6 Rx4_Rate_select Software rate select. Rx Channel 4 LSB - O O O 
5 Rx3_Rate_select Software rate select. Rx Channel 3 MSB - O O O 
4 Rx3_Rate_select Software rate select. Rx Channel 3 LSB - O O O 
3 Rx2_Rate_select Software rate select. Rx Channel 2 MSB - O O O 
2 Rx2_Rate_select Software rate select. Rx Channel 2 LSB - O O O 
1 Rx1_Rate_select Software rate select. Rx Channel 1 MSB - O O O 
0 Rx1_Rate_select Software rate select. Rx Channel 1 LSB - O O O 
88 7 Tx4_Rate_select Software rate select. Tx Channel 4 MSB - O O O 
6 Tx4_Rate_select Software rate select. Tx Channel 4 LSB - O O O 
5 Tx3_Rate_select Software rate select. Tx Channel 3 MSB - O O O 
4 Tx3_Rate_select Software rate select. Tx Channel 3 LSB - O O O 
3 Tx2_Rate_select Software rate select. Tx Channel 2 MSB - O O O 
2 Tx2_Rate_select Software rate select. Tx Channel 2 LSB - O O O 
1 Tx1_Rate_select Software rate select. Tx Channel 1 MSB - O O O 
0 Tx1_Rate_select Software rate select. Tx Channel 1 LSB - O O O 
89 – 
92 All Reserved Prior to Rev 2.10 used for SFF-8079 – now 
deprecated. 
- - - - 
93 7 SW Reset Software reset is a self-clearing bit that causes 
the module to be reset. The effect shall be the 
same as asserting the ResetL signal for the hold 
time in the module hardware specification, 
followed by its deassertion  
0b=not in reset  
1b=trigger a reset  
See Page 00h Byte 221 bit 0 for implementation 
indicator  
- O O O 
6-4 Reserved  - - - - 
3 High Power Class 
Enable (Class 8) 
When set to 1 enables Power Class 8 if listed in 
Byte 129.  When cleared to 0, modules with 
Power Class 8 shall consume less than the 
power specified by bit 2, but are not required to 
be fully functional. Refer to Table 6-11.  Default 
= 0. 
- O O O 
2 High Power Class 
Enable (Classes 5-
7) 
When set to 1 enables Power Classes 5 to 7 if 
listed in Byte 129.  When cleared to 0, modules 
with Power Classes 5 to 8 shall consume less 
than 3.5 W, but are not required to be fully 
functional. Refer to Table 6-11.  Default = 0. 
- O O O 
1 Power set For QSFP+/QSFP28: 
Power set to Low Power Mode (Power Class 1). 
Default 0. 
For microQSFP: 
Redefined as Low Power Mode. Default=1. 
- R R R 


Byte Bit Name Description PC AC AO SM 
0 Power override Override of LPMode/TxDis pad state to allow 
power mode setting by software. Default 0. 
- R R R 
94-
97 
All Reserved  - - - - 
98 7 Tx4_CDR_control Channel 4 Tx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
6 Tx3_CDR_control Channel 3 Tx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
5 Tx2_CDR_control Channel 2 Tx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
4 Tx1_CDR_control Channel 1 Tx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
3 Rx4_CDR_control Channel 4 Rx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
2 Rx3_CDR_control Channel 3 Rx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
1 Rx2_CDR_control Channel 2 Rx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
0 Rx1_CDR_control Channel 1 Rx CDR Control  
(1b = CDR on, 0b = CDR off) 
- O O O 
99 7-2 Reserved  - - - - 
1 LP/TxDis ctrl LPMode/TxDis input signal control.  See SFF-
8679 for a complete description. 
0b = LPMode 
1b = TxDis 
- O O O 
0 IntL/LOSL ctrl IntL/LOSL output signal control. See SFF-8679 
for a complete description. 
0b = IntL 
1b = LOSL 
- O O O 

For transceivers with CDR capability, setting the CDR to ON engages the internal retiming function. Setting the CDR 
to OFF enables an internal bypassing mode, which directs traffic around the internal CDR. The two most common 
reasons to turn a CDR off (i.e. internally bypass it) are to run at rates not supported by a particular CDR or to save 
the thermal power in applications where CDR jitter mitigation is not required. Jitter specifications of the high-speed 
interfaces are outside the scope of this specification. 

QSFP+ and QSFP28 modules have the LPMode input signal (see SFF-8679) that can be used by the host system to 
force the module into Low Power Mode.  Low Power Mode for those modules is defined as maximum power 
consumption of 1.5W.  If the LPMode input signal is pulled low by the host system, the module is then capable of 
entering High Power Mode.  The maximum power consumption in High Power Mode depends on the module Power 
Class as advertised in the Extended Identifier (see 6.3.2), Page 00h, byte 129, bits 1-0 and 7-6.  

The operation of the LPMode input signal can be overridden by the host writing a ‘1’ to byte 93, bit 0.  In that case, 
the function of the LPMode input signal is replaced by byte 93, bit 1. 

SFF-8436 has 4 power classes from 1.5 to 3.5 W.  Only bits 7-6 are used to define those power classes.  At revision 
1.9 of this specification, 3 new higher power classes, 4.0 W, 4.5 W , and 5.0 W were added. These power classes, 
designated power classes 5, 6 and 7, are designated using bits 1-0 of the Extended Identifier byte, page 00h byte 
129.  In order to protect legacy host systems designed to support only the original 4 power classes, the High Power 
Class Enable control was defined at byte 93, bit 2.  Modules in power classes 5, 6, 7 or 8 are required to limit power 
consumption to no more than a power class 4 module if the High Power Class Enable, byte 93 bit 2 control is not 
set.  They are not required to be functional in this situation.  



Starting with SFF -8636 Rev 2.10, a new Power Class 8 is introduced.  It is enabled using byte 93, bit 3 and  is 
advertised using upper page 00h, byte 129, bit 5.  Power Class 8 modules use byte 107 to advertise the maximum 
power consumption of the module.  For Power Class 8 advertising see page 00h, byte 129.  Modules in power class 
8 are required to limit power consumption to no more than a power class 7 module if the High Power Class Enable, 
byte 93 bit 3 control is not set.  They are not required to be functional in this situation. 

A truth table for the power controls in byte 93 bits 0, 1, 2 and 3, is shown in Table 6-11.  

Power class limits and controls for microQSFP modules are different from the description here.  Refer to the  MSA 
specification for details. 

(PDF p.39)

Table 6-11  Truth table for enabling power classes (Page 00h Byte 93) 
(The maximum consumption limits in this table are based on SFF-8679 for QSFP modules). 

LPMode (*) Power 
Override B93 
bit 0 
Power Set 
B93 bit 1 
High Pwr 
Class Enable 
B93 bit2 
High Pwr 
Class Enable 
B93 bit3 
Enabled 
Power 
Classes 
0 0 X 0 0 1 to 4 
0 0 X 1 0 1 to 7 
0 0 X 1 1 1 to 8 
0 0 X 0 1 8 
1 0 X X X 1 

X 1 0 0 0 1 to 4 
X 1 0 1 0 1 to 7 
X 1 0 1 1 1 to 8 
X 1 0 0 1 8 
X 1 1 X X 1 

(*) LPMode is a signal carried on a dual -purpose contact .  When the dual -purpose contact is not 
programmed as LPMode, the module behaves as though LPMode = 0.  Refer to SFF-8679 section 5.3.3 for 
details. 
6.2.7 Rate Select 
Rate Select is an optional control used to limit the receiver bandwidth for compatibility with multiple signaling rates. 
In addition, rate selection allows the transmitter and receiver to be tuned for specific rates. For more information, 
see Appendix A Rate Select and Configuration for Multi-rate Modules (Informative)  


The free side device shall implement one of two options: 

a) Provide no support for rate selection 
b) Rate selection using extended rate select 

6.2.7.1 No Rate Selection Support 
When no rate selection is supported, (Page 00h Byte 221 bits 2 and 3) have a value of 0 and Options (Page 00h 
Byte 195 bit 5) has a value of 0. Lack of implementation does not indicate a lack of simultaneous compliance with 
multiple standard rates. See 6.3.4 for the description of how compliance with particular standards should be 
determined.  


6.2.7.2 Extended Rate Selection 
When Page 00h Byte 195 bit 5 is 1 and Rate Select declaration bits (Page 00h Byte 221 bits 2 and 3) have the 
values of 0 and 1 respectively and at least one of the bits in the Extended Rate Compliance byte (Page 00h Byte 
141) has a value of one, the free s ide device supports extended rate select. For extended rate selection, two bits 
are assigned to each receiver in Byte 87 (Rxn_Rate_Select) and two bits for each transmitter in Byte 88 
(Txn_Rate_Select) to specify up to four rates. See Table 6-12 for the functionality when Byte 141 bits 0-1 are set. 
All other values of the Extended Rate Compliance byte are reserved. 

(PDF p.40)

Table 6-12  xN_Rate_Select with Extended Rate Selection 
xN_Rate_Select 
(MSB Value) 
xN_Rate_Select 
(LSB Value) Description 
Version 1 - Page 00h Byte 141 Bit 0 = 1 
0 0 Optimized for signaling rates less than 2.2 GBd 
0 1 Optimized for signaling rates from 2.2 up to 6.6 GBd 
1 0 Optimized for 6.6 GBd signaling rates and above 
1 1 Reserved 
Version 2 - Page 00h Byte 141 Bit 1 = 1 
0 0 Optimized for signaling rates less than 12 GBd 
0 1 Optimized for signaling rates from 12 up to 24 GBd 
1 0 Optimized for signaling rates from 24 up to 26 GBd 
1 1 Optimized for 26 GBd signaling rates and above 




6.2.8 Free Side Device Indicators and Channel Masks (Page 00h, Bytes 100-106) 
The fixed side may control which flags result in a hardware interrupt by setting high individual bits from a set of 
masking bits in Page 00h Bytes 100-104 for free side device flags, and Page 03h Bytes 242 -251 for channel flags. 
See Table 6-13 and Table 6-35. A 1 value in a masking bit prevents the assertion of the hardware interrupt pin, if 
one exists, by the corresponding latched flag bit. Masking bits are volatile and startup with all unmasked (masking 
bits 0). 

The mask bits may be used to prevent continued interruption from on -going conditions, which would otherwise 
continually reassert the hardware interrupt pin. A mask bit is allocated for each flag bit.  

(PDF p.41)

Table 6-13  Hardware Interrupt Pin Masking Bits (Page 00h Bytes 100-106) 
Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
100 7 M-Tx4 LOS Mask Masking bit for Tx4 LOS indicator C C C C 
6 M-Tx3 LOS Mask Masking bit for Tx3 LOS indicator C C C C 
5 M-Tx2 LOS Mask Masking bit for Tx2 LOS indicator C C C C 
4 M-Tx1 LOS Mask Masking bit for Tx1 LOS indicator C C C C 
3 M-Rx4 LOS Mask Masking bit for Rx4 LOS indicator C C C C 
2 M-Rx3 LOS Mask Masking bit for Rx3 LOS indicator C C C C 
1 M-Rx2 LOS Mask Masking bit for Rx2 LOS indicator C C C C 
0 M-Rx1 LOS Mask Masking bit for Rx1 LOS indicator C C C C 
101 7 M-Tx4 Adapt EQ Fault Mask  Masking bit for Tx4 Adaptive EQ fault C C C C 
6 M-Tx3 Adapt EQ Fault Mask Masking bit for Tx3 Adaptive EQ fault C C C C 
5 M-Tx2 Adapt EQ Fault Mask Masking bit for Tx2 Adaptive EQ fault C C C C 
4 M-Tx1 Adapt EQ Fault Mask Masking bit for Tx1 Adaptive EQ fault C C C C 
3 M-Tx4 Transmitter Fault Mask Masking bit for Tx4 Transmitter fault C C C R 
2 M-Tx3 Transmitter Fault Mask Masking bit for Tx3 Transmitter fault C C C R 
1 M-Tx2 Transmitter Fault Mask Masking bit for Tx2 Transmitter fault C C C R 
0 M-Tx1 Transmitter Fault Mask Masking bit for Tx1 Transmitter fault C C C R 
102 7 M-Tx4 CDR LOL Mask Masking bit for Tx4 CDR Loss of Lock C C C C 
6 M-Tx3 CDR LOL Mask Masking bit for Tx3 CDR Loss of Lock C C C C 
5 M-Tx2 CDR LOL Mask Masking bit for Tx2 CDR Loss of Lock C C C C 
4 M-Tx1 CDR LOL Mask Masking bit for Tx1 CDR Loss of Lock C C C C 
3 M-Rx4 CDR LOL Mask Masking bit for Rx4 CDR Loss of Lock C C C C 
2 M-Rx3 CDR LOL Mask Masking bit for Rx3 CDR Loss of Lock C C C C 
1 M-Rx2 CDR LOL Mask Masking bit for Rx2 CDR Loss of Lock C C C C 
0 M-Rx1 CDR LOL Mask Masking bit for Rx1 CDR Loss of Lock C C C C 
103 7 M-Temp High Alarm Masking bit for high-temperature alarm C C C C 
6 M-Temp Low Alarm Masking bit for low-temperature alarm C C C C 
5 M- Temp High Warning Masking bit for high-temperature warning C C C C 
4 M-Temp Low Warning Masking bit for low-temperature warning C C C C 
3-2 Reserved  - - - - 
1 M-TC readiness flag Masking bit for TC readiness flag 

C C C C 
0 Reserved  - - - - 
104 7 M-Vcc High alarm Masking bit for Vcc high alarm C C C C 
6 M-Vcc Low alarm Masking bit for Vcc low alarm C C C C 
5 M-Vcc High Warning Masking bit for Vcc high warning C C C C 


Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
4 M-Vcc Low Warning Masking bit for Vcc low warning C C C C 
3-0 Reserved  - - - - 
105-
106 
All Vendor Specific  - - - - 




6.2.9 Free Side Device Properties (Page 00h, Bytes 107-117) 
Byte 107 indicates the maximum module power consumption in 0.1 W increments. This field shall be populated if 
the module advertises Power Class 8 in Page 00h Byte 129 (see Table 6-16). However, non-Power Class 8 modules 
may also report their maximum module power consumption in this field. Modules that do not report their maximum 
power consumption shall populate this field with 00h. 

The unsigned 16-bit value in Bytes 108-109 indicates the propagation delay of the non-separable free side device. 
Byte 108 bit 7 is the most significant bit and Byte 109 bit 0 is the least significant. Each unit of the combined value 
corresponds to 10 ns with fractional values rounded up to the next unit. 

Byte 110 bits 7-4 specify the free-side device power consumption levels below 1.5 W. A value of 0000 shall indicate 
that a power consumption limit below 1.5 W is not available. A value of 0001 shall indicate the free-side device 
shall consume no more than 1 W, 0010 indicates no more than 0.75 W and 0011 indicates no more than 0.5 W.  

A value of 1 in Byte 110 bit 3 shall indicate that both ends of the free -side device comply with the SFF -8636 
specification. A value of 0 shall be utilized for all other cases including the use of other management interfaces 
specifications and separable applications where the free -side device ends and media can be physically separated 
from each other. Byte 110 bits 2 -0 indicate that the free-side device can operate properly from less than nomina l 
3.3 V on the Vcc pins. A value of 000 indicates the feature i s disabled. The free-side device shall operate properly 
from nominal 2.5 V with a value of 001 and nominal 1.8 V with a value of 010. 

The use of Bytes 111-112 is not defined in this specification.  

Byte 113 bits 3 -0 specify which channels of the free side device at the near end are implemented. A value of 0 
indicates that the channel is implemented and a value of 1 indicates that the channel is not implemented.  

Byte 113 bits 6 -4 are used to indicate what type of device(s) are implemented at the far end(s) of a cable or 
module. A separable free side device or a device that does not specify the far end implementation is coded 000.  

The ModSelL wait time fields define the minimum supported setup time for the ModSelL signal , defined as the 
elapsed time between host assertion of ModSelL and the start of a two-wire serial bus transaction and the required 
delay from completion of a two -wire serial bus transaction until the host can de -assert the ModSelL signal.  For 
example, if the module wait time is 1.6 ms, the mantissa field (bits 4-0) will be 11001b and the exponent field (bits 
7-5) will be 110b indicating six binary zeroes after the 11001b, for a net result of 11001000000b, or 1600 decimal. 

Host implementers should note that the host must use the worst -case ModSelL wait time for all modules on the 
same shared two-wire serial bus.  For example, when a new module is hot swapped onto the shared serial bus, the 
host must use the wait time specified in the hardware specification for all modules on that serial bus, until the 
supported ModSelL wait time for that new module can be identified. 

The secondary extended specification compliance code in Byte 116 identifies an electrical or optical interface that 
is not included in Table 6-17 Specification Compliance Codes, and is an additional supported specification relative 
to Page 00h, Byte 192 (see 6.3.23). 

An additional sub-type identifier in Byte 117 bits 7-4 can be used to provide information to the host on mechanical 
and thermal implementation. Refer to SFF-8024 for possible values and the hardware specification for more 
information on the listed sub -types. When applicable, the Fiber Face Type,  byte 117, bits 1-0 are used to identify 
the fiber face type for the specific connector type. The values are listed in SFF-8024. 

(PDF p.44)

Table 6-14  Free Side Device Properties (Page 00h Bytes 107-116) 
Byte Bit Name Description PC AC AO SM 
107 All Max Power 
Consumption 
Maximum power consumption of module.  
Unsigned integer with LSB = 0.1 W. 
O O O O 
108 All Propagation Delay 
MSB 
The most significant byte of propagation delay R R R O 
109 All Propagation Delay 
LSB 
The least significant byte of propagation delay R R R O 
110 7-4 Advanced Low 
Power Mode 
The code indicates maximum power consumption 
less than 1.5 W.  For SAS applications refer to SFF-
8449. 
0000 1.5W or higher 
0001 no more than 1 W 
0010 no more than 0.75 W 
0011 no more than 0.5 W 
R R R O 
3 Far Side Managed A value of 1 indicates that the far end is managed 
and complies with SFF-8636. 
R R R O 
2-0 Min Operating 
Voltage 
The code indicates nominal supply voltages lower 
than 3.3 V.  For SAS applications refer to SFF-8449. 
000 3.3 V 
001 2.5 V 
010 1.8 V 
R R R O 
111-
112 
All Assigned for use 
by PCI Express 
Used for: 
- The PCI Express External Cable Specification 
- The PCI Express OCuLink Specification 
- - - - 
113 7 Reserved  - - - - 
6-4 Far-End 
Implementation 
=000 Far end is unspecified 
=001 Cable with single far-end with 4 channels 
implemented, or separable module with a 4-
channel connector 
=010 Cable with single far-end with 2 channels 
implemented, or separable module with a 2-
channel connector 
=011 Cable with single far-end with 1 channel 
implemented, or separable module with a 1-
channel connector 
=100 4 far-ends with 1 channel implemented in 
each (i.e. 4x1 break out) 
=101 2 far-ends with 2 channels implemented in 
each (i.e. 2x2 break out) 
=110 2 far-ends with 1 channel implemented in 
each (i.e. 2x1 break out) 
R R R O 
3-0 Near-End 
Implementation 
Bit 0 =0 Channel 1 implemented 
        =1 Channel 1 not implemented 
Bit 1 =0 Channel 2 implemented 
       =1 Channel 2 not implemented 
Bit 2 =0 Channel 3 implemented 
       =1 Channel 3 not implemented 
Bit 3 =0 Channel 4 implemented 
       =1 Channel 4 not implemented 
R R R O 
114 7-4 Tx_TurnOn 
MaxDuration 
Tx_TurnOn_MaxDuration for microQSFP MSA.  
0000b=Not implemented. 
R R R R 
3-0 DataPathInit 
MaxDuration 
DataPathInit_MaxDuration for microQSFP MSA.  
0000b=Not implemented. 
R R R R 



6.2.10  Password Entry and Change (Page 00h, Bytes 119-126) 
Bytes 119-126 are reserved for an optional password entry function. The Password entry bytes are write-only and 
will be retained until power down, reset, or rewritten by fixed side. This function may be used to control read/write 
access to Vendor Specific Page 02h. Additionally, free side device vendors may use this function to implement write 
protection of Ser ial ID and other read-only information. Passwords may be supplied to and used by fixed side 
system manufacturers to limit write access in the User EEPROM Page 02h. 

Password access shall not be required to access free side device data in the lower memory Page 00h or in Upper 
Page 00h, 02h, and 03h. Note that multiple manufacturer passwords may be defined to allow selective access to 
read or write to various sections of memory as allowed above. 

Fixed side manufacturer and free side device manufacturer passwords shall be distinguished by the high order bit 
(bit 7, Byte 123). All fixed side manufacturer passwords shall fall in the range of 00000000h to 7FFFFFFFh and all 
free side device manufacturer passwords in the range of 80000000h to FFFFFFFFh. Fixed side system manufacturer 
passwords shall be initially set to 00001011h in new free side devices. 

Fixed side system manufacturer passwords may be changed by writing a new password in Bytes 119-122 when the 
correct current fixed side manufacture password has been entered in 123-126, with the high order bit being ignored 
and forced to a value of 0 in the  new password. The password entry field shall be set to 00000000h on power-up 
and reset. 
6.2.11  Page Select (Page 00h, Byte 127) 
Byte 127 is used to select the upper page. A value of 00h indicates upper memory Page 00h is mapped to Bytes 
128-255 and a value of 01h indicates that upper Page 01h if available is mapped to Bytes 128-255. Similarly, values 
of 02h, 03h, 20h, and 21h indicate which upper page is mapped to Bytes 128-255. If the host attempts to write a 
page select value which is not supported in a particular module, the Page Select byte will revert to 00h.  


Byte Bit Name Description PC AC AO SM 
115 7-5 ModSelL wait time 
exponent 
The ModSelL wait time is the mantissa x 
2^exponent expressed in microseconds.  In other 
words, the mantissa field is shifted up by the 
number of bits indicated in the exponent field (time 
= mantissa << exponent). 
A value of 00h indicates these fields are not 
implemented. 
O O O O 
4-0 ModSelL wait time 
mantissa 
116 All Secondary 
Extended Spec 
Compliance 
Secondary Extended Specification Compliance 
Codes (See SFF-8024 Transceiver Management) 
R R R R 
117 7-4 Transceiver Sub-
type 
Transceiver Sub-type code (See SFF-8024 
Transceiver Management) 
R R R R 
3-2 Reserved  R R R R 
1-0 Fiber Face Type Fiber Face Type code (See SFF-8024 Transceiver 
Management) 
R R R R 


6.3 Upper Page 00h 
Upper Page 00h consists of the Serial ID and is used for read-only identification information.  

(PDF p.46)

Table 6-15  Upper Page 00h Memory Map 
Byte Size Name Description P
C 
A
C 
A
O 
S
M 
128 1 Identifier  Identifier Type of free side device (See SFF -8024 
Transceiver Management) 
R R R R 
129 1 Ext. Identifier Extended Identifier of free side device. Includes 
power classes, CLEI codes, CDR capability (See 
Table 6-16) 
R R R R 
130 1 Connector Type Code for media connector type (See SFF -8024 
Transceiver Management) 
R R R R 
131-
138 
8 Specification 
Compliance 
Code for electronic or optical compatibility (See 
Table 6-17) 
R R R R 
139 1 Encoding Code for serial encoding algorithm. (See SFF -8024 
Transceiver Management) 
R R R R 
140 1 Signaling rate, 
nominal 
Nominal signaling rate, units of 100 MBd. For rate 
> 25.4 GBd, set this to FFh and use Byte 222. 
R R R R 
141 1 Extended Rate 
Select  
Compliance 
Tags for extended rate select compliance .  See 
Table 6-18. 
R R R R 
142 

1 Length (SMF)  Link length supported at the signaling rate in byte 
140 or page 00h byte 222, for SMF fiber in km *.  A 
value of 1 shall be used for reaches from 0 to 1 km.  
R R R R 
143 1 Length (OM3 50 
um) 
Link length supported at the signaling rate in byte 
140 or page 00h byte 222, for EBW 50/125 um fiber 
(OM3), units of 2 m * 
R R R R 
144 1 Length (OM2 50 
um) 
Link length supported at the signaling rate in byte 
140 or page 00h byte 222, for 50/125 um fiber 
(OM2), units of 1 m * 
R R R R 
145 1 Length (OM1 62.5 
um) or Copper 
Cable Attenuation 
Link length supported at the signaling rate in byte 
140 or page 00h byte 222, for 62.5/125 um fiber 
(OM1), units of 1 m  *, or copper cable attenuation 
in dB at 25.78 GHz. 
R R R R 
146 1 Length (passive 
copper or active 
cable or OM4 50 
um) 
Length of passive or active cable assembly (units of 
1 m) or link length supported at the signaling rate 
in byte 140 or page 00h byte 222, for  OM4 50/125 
um fiber (units of 2 m) as ind icated by Byte 147. 
See 6.3.12. 
R R R R 
147 1 Device technology  Device technology (Table 6-19 and Table 6-20). R R R R 
148-
163 
16 Vendor name Free side device vendor name (ASCII) R R R R 
164 1 Extended Module Extended Module codes for InfiniBand (See Table 
6-21 ) 
R R R R 
165-
167 
3 Vendor OUI Free side device vendor IEEE company ID R R R R 
168-
183 
16 Vendor PN  Part number provided by free side device  
vendor(ASCII) 
R R R R 
184-
185 
2 Vendor rev Revision level for part number provided by the 
vendor(ASCII) 
R R R R 


Byte Size Name Description P
C 
A
C 
A
O 
S
M 
186-
187 
2 Wavelength or 
Copper Cable 
Attenuation 
Nominal laser wavelength (wavelength=value/20 in 
nm) or copper cable attenuation in dB at 2.5 GHz 
(Byte 186) and 5.0 GHz (Byte 187) 
R R R R 
188-
189 
2 Wavelength 
tolerance or 
Copper Cable 
Attenuation 
The range of laser wavelength (+/ - value) from 
nominal wavelength. (wavelength Tol. =value/200 
in nm) or copper cable attenuation in dB at 7.0 GHz 
(Byte 188) and 12.9 GHz (Byte 189) 
R R R R 
190 1 Max case temp. Maximum case temperature R R R R 
191 1 CC_BASE Check code for base ID fields (Bytes 128-190) R R R R 
192 1 Link codes Extended Specification Compliance Codes (See SFF-
8024) 
R R R R 
193-
195 
3 Options Optional features implemented. See Table 6-22. R R R R 
196-
211 
16 Vendor SN Serial number provided by vendor (ASCII) R R R R 
212-
219 
8 Date Code Vendor's manufacturing date code R R R R 
220 1 Diagnostic 
Monitoring Type 
Indicates which type of diagnostic monitoring is 
implemented (if any) in the free side device. Bit 1,0 
Reserved. See Table 6-24. 
R R R R 
221 1 Enhanced Options  Indicates which optional enhanced features are 
implemented in the free side device. See Table 
6-25. 
R R R R 
222 1 Baud Rate, 
nominal 
Nominal baud rate per channel, units of 250 MBd. 
Complements Byte 140. See Table 6-26. 
R R R R 
223 1 CC_EXT Check code for the Extended ID Fields (Bytes 192 -
222)  
R R R R 
224-
255 
32 Vendor Specific  Vendor Specific EEPROM - - - - 
* A value of zero means that the free side device does not support the specified technology or that the length 
information must be determined from the free side device technology. 



6.3.1 Identifier (00h 128) 
The Identifier Values at Byte 128 specify the physical device described by the serial information. This value shall 
be included in the serial data. These values are maintained in the Transceiver Management section of SFF-8024. 

6.3.2 Extended Identifier (00h 129) 
The extended identifier provides additional information about the free side device. For example, the identifier 
indicates if the free side device contains a CDR function and identifies the power consumption class it belongs to.  

Power classes 5, 6 and 7 were added in rev 1.9 of this specification to enable modules requiring more than 3.5W 
of consumption. However, legacy systems were designed for a maximum of 3.5W. To ensure that those systems 
were not harmed by power classes 5, 6 or 7 a lockout feature was added in Byte 93 bit 2 to enable high power 
mode for those modules. A legacy system does not know about Byte 129 bits 1-0 or about Byte 93 bit 2. New 
systems know about both and can configure power class 5 through 7 support accordingly. The power class 
identifiers specify maximum power consumption over operating conditions and life with all supported settings set 
to worst case values. 

Power Class 8 is introduced by rev 2.10 of this specification.  Class 8 modules advertise a fine-grained value of 
power consumption in Page 00h, Byte 107. See SFF-8679 for QSFP+/QSFP28 power consumption values. If byte 
129, bit 5 is set a module may also indicate one of the other power classes using bits 7-6 and 1-0, if it complies 
with that class.  It should set bits 7-6 and 1-0 to all 1’s if the maximum power consumption is greater than or 
equal to Power Class 7. 

(PDF p.48)

Table 6-16  Extended Identifier Values (Page 00h Byte 129) 
Bit Device Type 
7-6 
00: Power Class 1 (1.5 W max.) 
01: Power Class 2 (2.0 W max.) 
10: Power Class 3 (2.5 W max.) 
11: Power Class 4 (3.5 W max.) and Power Classes 5, 6 or 7 
5 Power Class 8 implemented (Max power declared in byte 107) 
4 0: No CLEI code present in Page 02h 
1: CLEI code present in Page 02h 
3 0: No CDR in Tx, 1: CDR present in Tx 
2 0: No CDR in Rx, 1: CDR present in Rx 
1-0 
00: Power Classes 1 to 4 
01: Power Class 5 (4.0 W max.) See Byte 93 bit 2 to enable. 
10: Power Class 6 (4.5 W max.) See Byte 93 bit 2 to enable. 
11: Power Class 7 (5.0 W max.) See Byte 93 bit 2 to enable. 

6.3.3 Connector Type (00h 130) 
The Connector Type entry at Page 00H Byte 130 indicates the connector type for the separable portion of the free 
side device (see 4.3.2). This value shall be included in the serial data. These values are maintained in the 
Transceiver Management section of SFF-8024. 



6.3.4 Specification Compliance (00h 131-138) 
The bit significant indicators define the electronic or optical interfaces that are supported by the free side device. 
At least one bit shall be set in this field, and if more than one bit is applicable (as in the case of Fibre Channel), all 
shall be set accordingly. Except where stated, the interface supports 4 lanes of the standard. 

(PDF p.49)

Table 6-17  Specification Compliance Codes (Page 00h Bytes 131-138) 
Byte Bit Module Capability 
10/40G/100G Ethernet Compliance Codes 
131 7 Extended: See section 6.3.23. The Extended Specification Compliance Codes are maintained 
in the Transceiver Management section of SFF-8024. 
6 10GBASE-LRM 
5 10GBASE-LR 
4 10GBASE-SR 
3 40GBASE-CR4 
2 40GBASE-SR4 
1 40GBASE-LR4 
0 40G Active Cable (XLPPI) 
SONET Compliance Codes 
132 7-3 Reserved 
2 OC 48, long reach 
1 OC 48, intermediate reach 
0 OC 48 short reach 
SAS/SATA Compliance Codes 
133 7 SAS 24.0 Gbps 
6 SAS 12.0 Gbps 
5 SAS 6.0 Gbps 
4 SAS 3.0 Gbps 
3-0 Reserved 
Gigabit Ethernet Compliance Codes 
134 7-4 Reserved 
3 1000BASE-T 
2 1000BASE-CX 
1 1000BASE-LX 
0 1000BASE-SX 
Fibre Channel Link Length 
135 7 Very long distance (V) 
6 Short distance (S) 
5 Intermediate distance (I) 
4 Long distance (L) 
3 Medium (M) 
Fibre Channel Transmitter Technology 
135 2 Reserved 
1 Longwave laser (LC) 
0 Electrical inter-enclosure (EL) 
136 7 Electrical intra-enclosure 
6 Shortwave laser w/o OFC (SN) 
5 Shortwave laser w OFC (SL) 
4 Longwave Laser (LL) 
3-0 Reserved 
Fibre Channel Transmission Media 
137 7 Twin Axial Pair (TW) 
6 Shielded Twisted Pair (TP) 


Byte Bit Module Capability 
5 Miniature Coax (MI) 
4 Video Coax (TV) 
3 Multi-mode 62.5 um (M6) 
2 Multi-mode 50 um (M5) 
1 Multi-mode 50 um (OM3) 
0 Single Mode (SM) 
Fibre Channel Speed 
138 7 1200 MBps (per channel) 
6 800 MBps 
5 1600 MBps (per channel) 
4 400 MBps 
3 3200 MBps (per channel) 
2 200 MBps 
1 Extended: See section 6.3.23. The Extended Specification Compliance Codes are maintained 
in the Transceiver Management section of SFF-8024. 
0 100 MBps 

6.3.5 Encoding (00h 139) 
The Encoding Values at Page 00h Byte 139 indicate the serial encoding mechanism for the high -speed serial 
interface. The value shall be contained in the serial data. These values are maintained in the Transceiver 
Management section of SFF-8024. 
6.3.6 Nominal Signaling Rate (00h 140) 
The nominal signaling rate per channel (BR, nominal) is specified in units of 100 Megabaud in byte 140 and in units 
of 250 Megabaud in byte 222. The baud rate includes overhead necessary to encode and delimit the signal as well 
as symbols carrying data information. A value of 0 indicates the baud rate is not specified and must be determined 
from the module technology. A value of FFh in byte 140 means the baud rate exceeds 25.4 GBd and byte 222 must 
be used to determine nominal baud rate. The actual information transfer rate will depend on the encoding of the 
data, as defined by the encoding value (byte 139). 
6.3.7 Extended Rate Select Compliance (00h 141) 
The Extended Rate Select Compliance field is used to allow a single free side device the flexibility to comply with 
single or multiple Extended Rate Select definitions. A definition is indicated by the presence of a '1' in the specified 
bit. If exclusive, non-overlapping definitions are used, Page 00h Byte 141 will allow compliance to 8 distinct multi -
rate definitions. 

(PDF p.50)

Table 6-18  Extended Rate Select Compliance Tag Assignment (Page 00h Byte 141)  
Byte Bits Description 
141 7-2 Reserved 
1-0 Rate Select Version.  
This functionality is different from SFF-8472 and SFF-8431. 
10b:  Rate Select Version 2 
01b:  Rate Select Version 1 
00b, 11b: Reserved 
Note: See 6.2.7 for further details of the use of this field 

6.3.8 Length (Standard SM Fiber) -km (00h 142) 
In addition to EEPROM data from original GBIC definition, this value specifies the link length that is supported by a 
separable module free side device while operating in compliance with the applicable standards using single mode 
fiber. Supported link length is as specified in INF -8074. The value is in units of kilometers. A value of zero means 


that the free side device does not support single mode fiber or that the length information must be determined 
from the free side device technology. For all cable assemblies, including active optical cables, the value shall be 
zero. 
6.3.9 Length (OM3) (00h 143) 
This value specifies the link length that is supported by a separable module free side device while operating in 
compliance with the applicable standards using 2000 MHz*km (850 nm) extended bandwidth 50-micron multi-mode 
fiber. The value is in units of 2 meters. A value of zero means that the free side device does not support OM3 fiber 
or that the length information must be determined from the free side device technology. For all cable assemblies, 
including active optical cables, the value shall be zero. 

6.3.10   Length (OM2) (00h 144) 
This value specifies the link length that is supported by a separable module free side device while operating in 
compliance with the applicable standards using 500 MHz*km (850 nm and 1310 nm) 50 -micron multi-mode fiber. 
The value is in units of 1 meter. A value of zero means that the free side device does not support OM2 fiber or that 
the length information must be determined from the free side device technology. For all cable assemblies, including 
active optical cables, the value shall be zero. 
6.3.11   Length (OM1) or Copper Cable Attenuation (00h 145) 
This value specifies the link length that is supported by a separable module free side device while operating in 
compliance with the applicable standards using 200  MHz*km (850 nm) and 500  MHz*km (1310 nm) 62.5 -micron 
multi-mode fiber. The value is in units of 1 meter. A value of zero means that the free side device does not support 
OM1 fiber or that the length information must be determined from the free side device technology.  

For copper cable assemblies, where page 00h byte 147 bits 7-4 are 1010b, 1011b, 1101b or 1111b, this register is 
used to record the cable attenuation (or apparent attenuation from the near end of the cable for active cables) at 
25.78 GHz in units of 1 dB.  An indication of 0 dB attenuation refers to the case where the attenuation is not known 
or is unavailable.  For active optical cables or copper cables not listed in this paragraph, the value shall be zero. 

6.3.12   Length: Cable Assembly or Optical Fiber (OM4) (00h 146) 
If a separable module (as indicated by a value other than 23h in Byte 130) free side device transmitter technology 
is 850nm VCSEL (indicated by Byte 147 bits 7-4) then this value specifies the link length supported while operating 
in compliance with the applicable standards using 4700 MHz*km (850nm) extended bandwidth 50 -micron multi-
mode fiber (OM4). The value is in units of 2 meters.  

Otherwise, this value specifies the link length of a Cable assembly (copper or AOC) in units of 1 meter. Link length 
is as specified in the INF-8074. Link lengths less than 1 meter shall indicate 1 meter.  

A value of zero means the free side device is not a cable assembly or the length information must be determined 
from the separable free side device technology. A value of 255 means a separable module VCSEL free side device 
supports a link length greater than 508 meters or the cable assembly has a link length greater than 254 meters. 
6.3.13   Device Technology (00h 147) 
Aspects of the device or cable technology used are described by the Device Technology byte.  An active optical 
cable may be distinguished from a separable module by reading Byte 130 (Connector Type). 

(PDF p.52)

Table 6-19  Device Technology (Page 00h Byte 147) 
Bits Description 
7-4 Transmitter technology (See Table 6-20) 
3 0: No wavelength control 
1: Active wavelength control 
2 0: Uncooled transmitter device 
1: Cooled transmitter 
1 0: Pin detector 
1: APD detector 
0 0: Transmitter not tunable 
1: Transmitter tunable 

(PDF p.52)

Table 6-20  Transmitter Technology (Page 00h Byte 147 Bits 7-4) 
Value Description 
0000b 850 nm VCSEL 
0001b 1310 nm VCSEL 
0010b 1550 nm VCSEL  
0011b 1310 nm FP 
0100b 1310 nm DFB 
0101b 1550 nm DFB 
0110b 1310 nm EML 
0111b 1550 nm EML 
1000b Other / Undefined 
1001b 1490 nm DFB 
1010b Copper cable unequalized 
1011b Copper cable passive equalized 
1100b Copper cable, near and far end limiting active equalizers 
1101b Copper cable, far end limiting active equalizers 
1110b Copper cable, near end limiting active equalizers 
1111b Copper cable, linear active equalizers 

6.3.14   Vendor Name (00h 148-163) 
The vendor name is a 16-character field that contains ASCII characters, left -aligned and padded on the right with 
ASCII spaces (20h). The vendor name shall be the full name of the corporation, a commonly accepted abbreviation 
of the name of the corporation , the SCSI company code for the corporation, or the stock exchange code for the 
corporation. At least one of the vendor name or the vendor OUI fields shall contain valid serial data.  
6.3.15   Extended Module Codes (00h 164) 
The Extended Module Codes define the electronic or optical interfaces for InfiniBand that are supported by the free 
side device. 

(PDF p.53)

Table 6-21  Extended Module Code Values (Page 00h Byte 164) 
Byte Bit Module Code 
InfiniBand Data Rate codes 
164 7-6 Reserved 
5 HDR 
4 EDR 
3 FDR 
2 QDR 
1 DDR 
0 SDR 

6.3.16   Vendor Organizationally Unique Identifier Field (00h 165-167) 
The vendor organizationally unique identifier field (vendor OUI) is a 3 -byte field that contains the IEEE Company 
Identifier for the vendor. A value of all zero in the 3-byte field indicates that the Vendor OUI is unspecified. 
6.3.17   Vendor Part Number (00h 168-183) 
The vendor part number (vendor PN) is a 16-byte field that contains ASCII characters, left-aligned and padded on 
the right with ASCII spaces (20h), defining the vendor part number or product name. A value of all zero in the 16-
byte field indicates that the vendor PN is unspecified. 
6.3.18   Vendor Revision Number (00h 184-185) 
The vendor revision number (vendor rev) is a 2 -byte field that contains ASCII characters, left-aligned and padded 
on the right with ASCII spaces (20h), defining the vendor's product revision number. A value of all zero in the field 
indicates that the vendor Rev is unspecified. 
6.3.19   Wavelength or Copper Cable Attenuation (00h 186-187) 
For optical free side devices, this parameter identifies the nominal transmitter output wavelength at room 
temperature. This parameter is a 16-bit hex value with Byte 186 as high order byte and Byte 187 as low order byte. 
The laser wavelength is equal to t he 16-bit integer value divided by 20 in nm (units of 0.05 nm). This resolution 
should be adequate to cover all relevant wavelengths yet provide enough resolution for all expected DWDM 
applications. For an accurate representation of controlled wavelength applications, this value should represent the 
center of the guaranteed wavelength range.  

If the free side device is identified as copper cable these registers are used to define the cable attenuation. An 
indication of 0 dB attenuation refers to the case where the attenuation is not known or is unavailable.  

Byte 186 (00-FFh) is the copper cable attenuation at 2.5 GHz in units of 1 dB. 

Byte 187 (00-FFh) is the copper cable attenuation at 5.0 GHz in units of 1 dB. 
6.3.20   Wavelength Tolerance or Copper Cable Attenuation (00h 188-189) 
The guaranteed tolerance of transmitter output wavelength under all normal operating conditions. For copper cable 
assemblies, the value is zero. This parameter is a 16 -bit value with Byte 188 as high order byte and Byte 189 as 
low order byte. The laser wavelength is equal to the 16-bit integer value divided by 200 in nm (units of 0.005 nm). 
Thus, the following two examples: 

Example 1: 

10GBASE-LR Wavelength Range = 1260 to 1355 nm 
Nominal Wavelength in Bytes 186-187 = 1307.5 nm. 
Represented as INT(1307.5 nm * 20) = 26150 = 6626h 
Wavelength Tolerance in Bytes 188-189 = 47.5 nm. 
Represented as INT(47.5 nm * 200) = 9500 = 251Ch 



Example 2: 

ITU-T Grid Wavelength = 1534.25 nm (195.4 THz) with 0.236 nm (30 GHz) Tolerance  
Nominal Wavelength in Bytes 186-187 = 1534.25 nm. 
Represented as INT(1534.25 nm * 20) = 30685 = 77DDh 
Wavelength Tolerance in Bytes 188-189 = 0.236 nm. 
Represented as INT(0.236 nm * 200) = 47 = 002Fh 

If the free side device is identified as copper cable these registers are used to define the cable attenuation. An 
indication of 0 dB attenuation refers to the case where the attenuation is not known or is unavailable.  

Byte 188 (00-FFh) is the copper cable attenuation at 7.0 GHz in units of 1 dB. 

Byte 189 (00-FFh) is the copper cable attenuation at 12.9 GHz in units of 1 dB. 
6.3.21   Maximum Case Temperature (00h 190) 
This parameter allows specification of a maximum case temperature other than the standard 70C. Maximum case 
temperature is an 8-bit value in degrees C. A value of 00h indicates 70C. 
6.3.22   CC_BASE (00h 191) 
The check code is a 1 -byte code that can be used to verify that the first 63 bytes of serial information in the free 
side device are valid. The check code shall be the low order 8 bits of the sum of the contents of all the bytes from 
128 to 190, inclusive. 
6.3.23   Extended Specification Compliance Codes (00h 192) 
The Extended Specification Compliance Codes in Byte 192 identify the electronic or optical interfaces which are not 
included in Table 6-17 Specification Compliance Codes . These values are maintained in the Transceiver 
Management section of SFF-8024 
6.3.24   Options (00h 193-195) 
The bits in the options field shall specify the options implemented in the free side device. 

Variable transceiver Tx input EQ and Rx output emphasis have been added, defined as the EQ and Emphasis 
capability designed into the transceiver in support of TP1a and TP4, respectively as defined in IEE802.3 Clause 86. 
Transceiver support of programmable EQ and Emphasis is found in Byte 193 bits 1 to 3 and shown below in Table 
6-22. The default host control mechanism is "Fixed Position Programmable", found in Page 03h, Bytes 234-237 and 
documented in Table 6-30, Table 6-32 and Table 6-33. If a transceiver supports "Adaptive EQ", defined as 
transceiver automatic internal control of EQ position setting (without host intervention), it can be so identified in 
Byte 193 bit 3. Adaptive EQ algorithms and periodicity are implementation specific. Control of "Adaptive EQ" is done 
using Upper Page 03h Byte 241 bits 3-0 (per channel controls). 

The magnitude of Tx input EQ and Rx output emphasis supported by the transceiver is identified in Page 03h Byte 
224. This applies to either Fixed Position Programmable or Adaptive EQ modes. 

CDR status and control functions are identified in Byte 194 bits 4 to 7. If Loss of Lock indicators (flags) are 
implemented bits 4 and 5 are set high. If CDR On/Off control is implemented bits 6 and 7 are set high. For 
transceivers with CDR capability, setting the CDR to ON engages the internal retiming function. Setting the CDR to 
OFF enables an internal bypassing mode, which directs traffic around the internal CDR. The two most common 
reasons to turn a CDR off (i.e. internally bypass it) are to run at rates not supported by a particular CDR or to save 
the thermal power in applications where CDR jitter mitigation is not required. 

(PDF p.55)

Table 6-22  Option Values (Page 00h Bytes 193-195) 
Byte Bit Description PC AC AO SM 
193 7 Reserved - - - - 
6 LPMode/TxDis input signal is configurable using byte 99, bit 1. See 
SFF-8679 for a complete description. 

5 IntL/RxLOSL output signal is configurable using byte 99, bit 0. See 
SFF-8679 for a complete description. 

4 Tx input adaptive equalizers freeze capable. 1 if implemented, else 0. R R R R 
3 Tx input equalizers auto-adaptive capable. 1 if implemented, else 0.  R R R R 
2 Tx input equalizers fixed-programmable settings. 1 if implemented, 
else 0. 
R R R R 
1 Rx output emphasis fixed-programmable settings. 1 if implemented, 
else 0. 
R R R R 
0 Rx output amplitude fixed-programmable settings. 1 if implemented, 
else 0. 
R R R R 
194 7 Tx CDR On/Off Control implemented. 1 if controllable, else 0.  R R R R 
6 Rx CDR On/Off Control implemented. 1 if controllable, else 0. R R R R 
5 Tx CDR Loss of Lock (LOL) flag implemented. 1 if implemented, else 0. R R R R 
4 Rx CDR Loss of Lock (LOL) flag implemented. 1 if implemented, else 0. R R R R 
3 Rx Squelch Disable implemented. 1 if implemented, else 0. R R R R 
2 Rx Output Disable implemented. 1 if implemented, else 0. R R R R 
1 Tx Squelch Disable implemented. 1 if implemented, else 0. R R R R 
0 Tx Squelch implemented. 1 if implemented, else 0. R R R R 
195 7 Memory Page 02 provided. 1 if implemented, else 0. R R R R 
6 Memory Page 01h provided. 1 if implemented, else 0. R R R R 
5 Rate select is implemented as defined in 6.2.7. If the bit is set to 1 
then refer to that section for multi-rate operation description. 
C C C C 
4 Tx_Disable is implemented and disables the serial output as defined by 
the relevant transmitter specification. 
R R R R 
3 Tx_Fault signal implemented. 1 if implemented, else 0 R R R R 
2 Tx Squelch implemented to reduce OMA coded 0, implemented to 
reduce Pave coded 1. 
R R R R 
1 Tx Loss of Signal implemented. 1 if implemented, else 0 R R R R 
0 Pages 20-21h implemented. Default = 0 (not implemented). R R R R 

6.3.25   Vendor Serial Number (00h 196-211) 
The vendor serial number (vendor SN) is a 16 -character field that contains ASCII characters, left-aligned and 
padded on the right with ASCII spaces (20h), defining the vendor's serial number for the free side device. A value 
of 0000h in the 16-byte field indicates that the vendor SN is unspecified. 

6.3.26   Date Code (00h 212-219) 
The date code is an 8 -byte field that contains the vendor's date code in ASCII characters. The date code is 
mandatory and shall be in the specified format. 

(PDF p.55)

Table 6-23  Date Codes (Page 00h Bytes 212-219) 
Byte Description PC AC AO SM 
212-213 ASCII code, two low order digits of the year. (00=2000) R R R R 
214-215 ASCII code digits of the month (01=Jan through 12=Dec R R R R 
216-217 ASCII code day of the month (01-31) R R R R 
218-219 ASCII code, Vendor Specific lot code, may be blank  R R R R 



6.3.27   Diagnostic Monitoring Type (00h 220) 
'Diagnostic Monitoring Type' is a 1 -byte field with 8 single bit indicators describing how diagnostic monitoring is 
implemented in the free side device.  

(PDF p.56)

Table 6-24  Diagnostic Monitoring Type (Page 00h Byte 220) 
Byte Bits Description PC AC AO SM 
220 7-6 Reserved - - - - 
5 Temperature monitoring implemented (0b=Not implemented 
or pre-Rev 2.8, 1b=Implemented) 
R R R R 
4 Supply voltage monitoring implemented (0b=Not 
implemented or pre-Rev 2.8, 1b=Implemented) 
R R R R 
3 Received power measurements type. 0=OMA, 1=Average 
Power 
R R R R 
2 Transmitter power measurement. 0=Not supported, 
1=Supported 
R R R R 
1-0 Reserved - - - - 

Digital Diagnostic Monitors monitor received power, bias current, supply voltage , and temperature. Additionally, 
alarm and warning thresholds must be written as specified in this document. Auxiliary monitoring fields are optional 
extensions to Digital Diagnostics. 

All digital monitoring values must be internally calibrated and reported in the units defined in 6.2.5. 

Bit 2 indicates whether a transmitted power measurement is supported. The indication is required, however, support 
of transmitter power measurement is optional (see Table 6-9). If the bit is set, the transmitted power measurement 
is supported, and the module will monitor the average optical power. If not, transmitted power measurement is 
not supported. 

Bit 3 indicates whether the received power measurement represents average input optical power or OMA. The 
indication is required, however, support of received power measurement is optional (see Table 6-9). If the bit is 
set, the average power is monitored. If not, received power measurement is not supported, or OMA is monitored.  



6.3.28 Enhanced Options (00h 221) 
See Table 6-25 for use of the Enhanced Options field. The state where the Rate Select declaration bits both have 
a value of 1 is reserved and should not be used. 

(PDF p.57)

Table 6-25  Enhanced Options (Page 00h Byte 221) 
Byte Bit Description PC AC AO SM 
221 

7-5 Reserved - - - - 
4 Initialization Complete Flag implemented. This flag was 
introduced in rev 2.5. When this bit is 1, the initialization 
complete flag at Byte 6 bit 0 is implemented independently of 
t_init. When this bit is 0, the initialization complete flag is 
either not implemented or if implemented has a response time 
less than t_init, max as specified for the module.  
R R R R 
3 Rate Selection Declaration: When this Declaration bit is 0 the 
free side device does not support rate selection. When this 
Declaration bit is 1, rate selection is implemented using 
extended rate selection. See 6.2.7.2 
R R R R 
2 This bit is reserved and reads 0.  It was used for SFF-8079 
support in revisions of this document before 2.10. 
- - - - 
1 TC readiness flag implemented. 
0= TC readiness flag not implemented. 
1= TC readiness flag is implemented. 
R R R R 
0 Software reset is implemented.  Use byte 93, bit 7. 
0b = not implemented. 
O O O O 

To enable baud rates in excess of 25.4 GBd, an extended baud rate field has been added in byte 222 to supplement 
the existing values in byte 140. Byte 140 contains baud rate at 100 MBd resolution, which is limited to 25.4  GBd. 
Byte 222 contains baud rate at 250 MBd resolution, enabling up to 63.5  GBd. A value of zero means this field is 
unspecified. 

(PDF p.57)

Table 6-26  Extended Baud Rate: Nominal (Page 00h Byte 222)  
Byte Bits Description PC AC AO SM 
222 7-0 Nominal baud rate, units of 250 MBd. See Byte 140 
description. 
R R R R 

6.3.29   Check Code Extension (00h 223) 
The check code is a 1-byte code that can be used to verify that the first 32 bytes of extended serial information in 
the free side device is valid. The check code shall be the low order 8 bits of the sum of the contents of all the bytes 
from 192 to 222, inclusive. 
6.3.30   Vendor Specific (00h 224-255) 
This area may contain Vendor Specific information, which can be read from the free side device. The data is read-
only. Page 00h Bytes 224-255 may be used for Vendor Specific ID functions. 



6.4 Upper Page 01h (Optional) 
Page 01h  was previously used for an Application Select Table specified in SFF-8079.  This feature is now considered 
obsolete and so starting with SFF-8636 rev 2.10 this use of the page is deprecated.  It is now reserved. 
6.5 Upper Page 02h (Optional) 
Page 02 is optionally provided as user-writable EEPROM. The fixed side may read or write this memory for any 
purpose. If Page 00h Byte 129 bit 4 is set, however, the first 10 bytes of Page 02h Bytes 128-137 are used to store 
the CLEI code for the free side device. 



6.6 Upper Page 03h (Optional) 
Upper Page 03h contains free side device thresholds, channel thresholds and masks, ability registers for the optional 
equalizer, emphasis and amplitude , and optional channel controls. See 6.6.1, 0, 6.6.3 and 6.6.4 for detailed 
descriptions of their use.  

(PDF p.59)

Table 6-27  Upper Page 03h Memory Map 
Byte  # Bytes Description Type 
128-175 48 Thresholds Read-Only 
176-223 48 Channel Thresholds Read-Only 
224 1 Tx EQ & Rx Emphasis Magnitude ID Read-Only 
225 1 Rx output amplitude support indicators Read-Only 
226-229 4 Control options advertising Read-Only 
230-241 12 Optional Channel Controls  Read/Write 
242-251 10 Channel Monitor Masks Read/Write 
252-255 4 Reserved Read/Write 

6.6.1 Free Side Device and Channel Thresholds (Page 03h, Bytes 128-223) 
Each monitor value has a corresponding high alarm, low alarm, high warning, and low warning thresholds. For each 
monitor that is implemented, high and low alarm thresholds are required. These factory -preset values allow the 
user to determine when a particular value is outside of normal limits as determined by the free side device 
manufacturer. It is assumed that these values will vary with different technologies and different implementations. 
These values are stored in read-only memory in Page 03h Bytes 128-223. 

(PDF p.59)

Table 6-28  Free Side Device and Channel Thresholds (Page 03h Bytes 128-223) 
Byte # 
Bytes 
Name Description PC AC AO SM 
128-129 2 Temp High Alarm MSB at lower byte address C C C C 
130-131 2 Temp Low Alarm MSB at lower byte address C C C C 
132-133 2 Temp High Warning MSB at lower byte address O O O O 
134-135 2 Temp Low Warning MSB at lower byte address O O O O 
136-143 8 Reserved  - - - - 
144-145 2 Vcc High Alarm MSB at lower byte address C C C C 
146-147 2 Vcc Low Alarm MSB at lower byte address C C C C 
148-149 2 Vcc High Warning MSB at lower byte address O O O O 
150-151 2 Vcc Low Warning MSB at lower byte address O O O O 
152-159 8 Reserved  - - - - 
160-175 16 Vendor Specific  - - - - 
176-177 2 Rx Power High Alarm MSB at lower byte address C C C C 
178-179 2 Rx Power Low Alarm MSB at lower byte address C C C C 
180-181 2 Rx Power High Warning MSB at lower byte address O O O O 
182-183 2 Rx Power Low Warning MSB at lower byte address O O O O 
184-185 2 Tx Bias High Alarm MSB at lower byte address C C C C 
186-187 2 Tx Bias Low Alarm MSB at lower byte address C C C C 
188-189 2 Tx Bias High Warning MSB at lower byte address O O O O 
190-191 2 Tx Bias Low Warning MSB at lower byte address O O O O 
192-193 2 Tx Power High Alarm MSB at lower byte address C C C C 
194-195 2 Tx Power Low Alarm MSB at lower byte address C C C C 
196-197 2 Tx Power High Warning MSB at lower byte address O O O O 
198-199 2 Tx Power Low Warning MSB at lower byte address O O O O 


Byte # 
Bytes 
Name Description PC AC AO SM 
200-207 8 Reserved Reserved thresholds for channel 
parameter set 4 
- - - - 
208-215 8 Reserved Reserved thresholds for channel 
parameter set 5 
- - - - 
216-223 8 Vendor Specific  - - - - 

The values reported in the Alarm and Warning Thresholds area may be typical values at some chosen nominal 
operating conditions and may be temperature compensated or otherwise adjusted when setting warning and/or 
alarm flags. Any threshold compensation or adjustment is Vendor Specific and optional. Refer to the vendor's data 
sheet for use of alarm and warning thresholds. 




6.6.2 Optional Equalizer, Emphasis and Amplitude Indicators (Page 03h, Bytes 224-229) 

(PDF p.61)

Table 6-29  Equalizer, Emphasis, Amplitude and Timing (Page 03h Bytes 224-229) 
Byte Bit Name Description PC AC AO SM 
224 7-
4 
Max Tx input 
equalization 
Max Tx input equalization supported (controls are in 
bytes 234-235 and codes are in Table 6-32) 
O O O O 
3-
0 
Max Rx output 
emphasis 
Max Rx output emphasis supported (controls are in 
bytes 236-237 and codes are in Table 6-33) 
O O O O 
225 7-
6 
Reserved  - - - - 
5-
4 
Rx output emphasis 
type 
=00b Peak-to-peak amplitude stays constant, or 
not implemented, or no information 
=01b Steady state amplitude stays constant stays 
constant 
=10b Average of peak-to-peak and steady state 
amplitudes stays constant =11b Reserved 
O O O O 
3 Rx output 
amplitude support 
=0 Amplitude 0011 not supported or no information  
=1 Amplitude 0011 supported (see Table 6-31) 
O O O O 
2 =0 Amplitude 0010 not supported or no information 
=1 Amplitude 0010 supported (see Table 6-31)  
O O O O 
1 =0 Amplitude 0001 not supported or no information  
=1 Amplitude 0001 supported (see Table 6-31) 
O O O O 
0 =0 Amplitude 0000 not supported or no information  
=1 Amplitude 0000 supported (see Table 6-31) 
O O O O 
226 All Reserved  - - - - 
227 7 Controllable Host-
Side FEC support 
=0 Module’s host-side FEC, if any, is not 
controllable by the host. 
=1 Module can terminate and generate FEC 
encoding from and to the host under control of the 
host.  
See Page 03h, Byte 230, bit 7 for the control bit. 
- O O O 
6 Controllable Media-
Side FEC support 
=0 Module’s media-side FEC, if any, is not 
controllable by the host. 
=1 Module can generate and terminate FEC 
encoding from and to the media under control of 
the host.  
See Page 03h, Byte 230, bit 6 for the control bit. 
- O O O 
5-
4 
Reserved  - - - - 
3 Tx Force Squelch 
Implemented 
0 = Tx Force Squelch not implemented 
1 = Tx Force Squelch implemented.  See page 03h, 
byte 231, bits 3-0 for control bits. 
- O O O 
2 RxLOSL Fast Mode 
Supported 
0 = RxLOSL fast mode is not supported. 
1 = Complies with timing requirements of SFF-8679 
optional RxLOSL fast mode. 
- O O O 
1 TxDis Fast Mode 
Supported 
0 = TxDis fast mode is not supported. 
1 = Complies with timing requirements of SFF-8679 
optional TxDis fast mode. 
- O O O 
0 Reserved   - - - - 
228 All Maximum TC 
stabilization time 
Maximum time for the TC to reach its target 
working point under worst-case conditions.  LSB = 
1 s. 
O O O O 
229 All Maximum CTLE 
settling time 
Maximum time needed by CTLE adaptive algorithm 
to converge to an appropriate value under worst-
O O O O 


6.6.3 Optional Channel Controls (Page 03h, Bytes 230-241) 
Upper Memory Page Control Bits are used to define the optional channel controls. 

(PDF p.62)

Table 6-30  Optional Channel Controls (Page 03h Bytes 230-241) 
Byte Bit Name Description PC AC AO SM 
case conditions.  LSB = 100 ms. 
Byte Bit Name Description PC AC AO SM 
230 7 Host-Side FEC enable Enables host-side FEC termination on 
the Tx electrical inputs and host-side 
FEC generation on the Rx electrical 
outputs.  0b = disable, 1b = enable.  
Default = 0. 
- O O O 
6 Media-Side FEC enable Enables media-side FEC generation on 
the Tx outputs and media-side FEC 
termination on the Rx inputs.  0b = 
enable, 1b = disable. Default = 0. 
- O O O 
5-0 Reserved  - - - - 
231 7-4 Reserved  - - - - 
3 Tx4 Force Squelch Software squelch of transmitter 
output, per media lane. Note that the 
transmitter output may be disabled, 
which overrides the behaviors of this 
control  
0b = No impact on Tx behavior  
1b = Tx output squelched  
See Page 03h Byte 227 bit 3 for 
implementation indicator. 
- O O O 
2 Tx3 Force Squelch - O O O 
1 Tx2 Force Squelch - O O O 
0 Tx1 Force Squelch - O O O 
232 All Reserved  - - - - 
233 




7-4 Reserved  - - - - 
3 Tx1AEFreeze Controls to freeze Tx input adaptive 
equalizers. 1 to freeze, else 0.  See 
page 00h byte 193 bit 4 for support 
indicator. 
O O O O 
2 Tx2AEFreeze O O O O 
1 Tx3AEFreeze O O O O 
0 Tx4AEFreeze O O O O 
234 7-4 Tx1 input equalizer control Tx input equalizer controls (see Page 
03h Byte 224 and Table 6-32) 
O O O O 
3-0 Tx2 input equalizer control O O O O 
235 7-4 Tx3 input equalizer control O O O O 
3-0 Tx4 input equalizer control O O O O 
236 7-4 Rx1 output emphasis control Rx output emphasis controls (see 
Page 03h Byte 224 and Table 6-33) 
O O O O 
3-0 Rx2 output emphasis control O O O O 
237 7-4 Rx3 output emphasis control O O O O 
3-0 Rx4 output emphasis control O O O O 
238 7-4 Rx1 output amplitude control Controls for Rx output differential 
amplitude. (See Table 6-31) 
O O O O 
3-0 Rx2 output amplitude control O O O O 
239 7-4 Rx3 output amplitude control O O O O 
3-0 Rx4 output amplitude control O O O O 
240 7 Rx4 SQ Disable Controls to disable squelch of Rx 
outputs. 
1 = Disabled, 0 = Enabled 
Default = 0. 
O O O O 
6 Rx3 SQ Disable O O O O 
5 Rx2 SQ Disable O O O O 
4 Rx1 SQ Disable O O O O 
3 Tx4 SQ Disable Controls to disable squelch of Tx 
outputs. 
1 = Disabled, 0 = Enabled 
O O O O 
2 Tx3 SQ Disable O O O O 
1 Tx2 SQ Disable O O O O 

(PDF p.63)

Table 6-31  Output Differential Amplitude Control (Page 03h Bytes 238-239) 
Value Receiver Output Amplitude  
No Output Equalization 
Nominal Units 
1xxxb 
Reserved 

0111b 
0110b 
0101b 
0100b 
0011b 600-1200 
mV (p-p) 0010b 400-800 
0001b 300-600 
0000b 100-400 

(PDF p.63)

Table 6-32  Tx Input Equalizer Controls (Page 03h Bytes 234-235) 
Value Transmitter Input Equalization  

Nominal Units 
11xxb Reserved  
1011b 
1010b 10 
dB 
1001b 9 
1000b 8 
0111b 7 
0110b 6 
0101b 5 
0100b 4 
0011b 3 
0010b 2 
0001b 1 
0000b 0 No EQ 

Byte Bit Name Description PC AC AO SM 
0 Tx1 SQ Disable Default = 0. O O O O 
241 7 Rx4 Output Disable Controls to disable Rx outputs. 
1 = Disabled, 0 = Enabled 
Default = 0. 
O O O O 
6 Rx3 Output Disable O O O O 
5 Rx2 Output Disable O O O O 
4 Rx1 Output Disable O O O O 
3 Tx4 adaptive equalization 
control 
Controls for Tx input adaptive 
equalizers. 
1b=Enable (default) 
0b=Disable (use manual EQ)  
See 00h 193 bit 3 for implementation 
indicator. 
- O O O 
2 Tx3 adaptive equalization 
control 
- O O O 
1 Tx2 adaptive equalization 
control 
- O O O 
0 Tx1 adaptive equalization 
control 
- O O O 

(PDF p.64)

Table 6-33  Rx Output Emphasis Controls (Page 03h Bytes 236-237) 
Value Receiver Output Emphasis  
At nominal Output Amplitude 
Nominal Units 
1xxxb Reserved  
0111b 7 
dB 
0110b 6 
0101b 5 
0100b 4 
0011b 3 
0010b 2 
0001b 1 
0000b 0 No Emphasis 

Output amplitude and output emphasis are defined at the appropriate test points defined by the relevant standard.  
There is an illustration of reference test points in SFF-8679. 

Because receiver emphasis settings can affect receiver output amplitude (and vice versa) Table 6-31 and Table 
6-33 define the variable parameter at a nominal condition of the other. For instance, Table 6-31 defines output 
amplitude at a zero output emphasis setting and Table 6-33 defines output emphasis at a nominal output amplitude 
setting (implementation dependent). The maximum emphasis supported is defined in section 0, Table 6-29 byte 
224. If an implementation does not support all levels up to and including the maximum, the nearest value shall be 
used. 

Squelch and output control functionality is optional. If implemented, squelch and output disable is controlled for 
each channel using Page 03h Bytes 231 and 240-241.  Writing a '1' in the Squelch Disable register (Page 03h Byte 
240) disables the squelch for the associated channel. Writing a '1' in the Output Disable register (Page 03h Byte 
241) disables the output of the associated channel. When a '1' is written in both registers for a channel, the 
associated output is disabled. The registers read all '0's upon power-up. Note that the Tx Forced Squelch controls 
in page 03h, byte 231, override the Tx Squelch Disable settings (see Table 6-30).  All other squelch functionality 
details are outside the scope of this document.   

(PDF p.64)

Table 6-34  Tx Squelch Truth Table 
Tx Force 
Squelch 
(Byte 231) 
Tx Squelch 
Disable 
(Byte 240) Output Amplitude 
1 x Squelched 
0 1 Normal 
0 0 Auto-squelch enabled if implemented (see page 00h, byte 194, bit 0). 




6.6.4 Channel Monitor Masks (Page 03h, Bytes 242-251) 

(PDF p.65)

Table 6-35  Channel Monitor Masks (Page 03h Bytes 242-251) 
Byte Bit Name Description PC AC AO SM 
242 7 M-Rx1 Power High Alarm Masking bits for Rx input power alarms and 
warnings. 
C C C C 
6 M-Rx1 Power Low Alarm C C C C 
5 M-Rx1 Power High Warning C C C C 
4 M-Rx1 Power Low Warning C C C C 
3 M-Rx2 Power High Alarm C C C C 
2 M-Rx2 Power Low Alarm C C C C 
1 M-Rx2 Power High Warning C C C C 
0 M-Rx2 Power Low Warning C C C C 
243 7 M-Rx3 Power High Alarm C C C C 
6 M-Rx3 Power Low Alarm C C C C 
5 M-Rx3 Power High Warning C C C C 
4 M-Rx3 Power Low Warning C C C C 
3 M-Rx4 Power High Alarm C C C C 
2 M-Rx4 Power Low Alarm C C C C 
1 M-Rx4 Power High Warning C C C C 
0 M-Rx4 Power Low Warning C C C C 
244 7 M-Tx1 Bias High Alarm Masking bits for Tx bias alarms and 
warnings. 
C C C C 
6 M-Tx1 Bias Low Alarm C C C C 
5 M-Tx1 Bias High Warning C C C C 
4 M-Tx1 Bias Low Warning C C C C 
3 M-Tx2 Bias High Alarm  C C C C 
2 M-Tx2 Bias Low Alarm C C C C 
1 M-Tx2 Bias High Warning C C C C 
0 M-Tx2 Bias Low Warning C C C C 
245 7 M-Tx3 Bias High Alarm C C C C 
6 M-Tx3 Bias Low Alarm C C C C 
5 M-Tx3 Bias High Warning C C C C 
4 M-Tx3 Bias Low Warning C C C C 
3 M-Tx4 Bias High Alarm C C C C 
2 M-Tx4 Bias Low Alarm C C C C 
1 M-Tx4 Bias High Warning C C C C 
0 M-Tx4 Bias Low Warning C C C C 
246 7 M-Tx1 Power High Alarm Masking bits for Tx output power alarms 
and warnings. 
C C C C 
6 M-Tx1 Power Low Alarm C C C C 
5 M-Tx1 Power High Warning C C C C 
4 M-Tx1 Power Low Warning C C C C 
3 M-Tx2 Power High Alarm  C C C C 
2 M-Tx2 Power Low Alarm C C C C 
1 M-Tx2 Power High Warning C C C C 
0 M-Tx2 Power Low Warning C C C C 
247 7 M-Tx3 Power High Alarm C C C C 
6 M-Tx3 Power Low Alarm C C C C 
5 M-Tx3 Power High Warning C C C C 
4 M-Tx3 Power Low Warning C C C C 
3 M-Tx4 Power High Alarm C C C C 
2 M-Tx4 Power Low Alarm C C C C 
1 M-Tx4 Power High Warning C C C C 
0 M-Tx4 Power Low Warning C C C C 


Byte Bit Name Description PC AC AO SM 
248-
249 
All Reserved Reserved channel monitor masks set 4 - - - - 
250-
251 
All Reserved Reserved channel monitor masks set 5 - - - - 




6.7 Upper Page 20h and Upper Page 21h (Optional) 

The Upper Page 20h and Upper Page 21h contain support for additional monitored parameters for modules that 
have PAM4 modulation and/or have optical transmission wavelengths on a DWDM grid. 

6.7.1 Overview 
Many additional parameters may be supported by a QSFP with advanced modulation techniques. Pages 20h and 
21h in the SFF -8436/SFF-8636 memory space are assigned for monitoring of these parameters. The basic 
monitoring techniques are the same as for other monitored parameters (i.e., they support current value, latched 
warning/alarm status, masks , and thresholds).  To indicate to the host device whether pages 20h and 21h are 
supported, page 00h byte 195 bit 0 is used. A value of 1b indicates that page 20h and 21h are supported as 
described in this section. A value of 0b indicates that pages 20h and 21h are not supported by the module.  

For a PAM4 signal, several additional parameters are very useful to determine the health of the module and the 
line environment. These include bit error ratio and frame error rate calculations, a signal -to-noise ratio 
measurement and a level transition measurement that char acterize the PAM eye, and a residual dispersion 
measurement. 

For a module implementing a Dense Wavelength Division Multiplexing optical interface, there is a significant benefit 
in providing access to additional diagnostic monitoring parameters specifically for a DWDM module. In DWDM the 
wavelength or frequency of t he laser is an extremely important parameter and monitoring it allows the health of 
the laser to be known. When a direct measurement of the error in the frequency is not available, the laser 
temperature deviation from the target is often used as a proxy. In addition, DWDM modules typically use a thermo-
electric cooler (TEC) to control the laser temperature. The current flowing through the TEC is a strong indicator of 
the health of the module. A warning or error indication in any of these parameters can be a n early indication of 
pending module failure. 

Other modules may require additional parameters to be defined in the future. 

It is expected that not all possible features will be supported by all modules or on all channels. To address this 
situation, this specification allows the module to determine which parameters are being monitored. Some 
parameters may be module-level in scope, and some may be channel-specific. This information is conveyed by the 
module to the host in the 2-byte parameter configuration registers (page 20h bytes 200-248). To indicate that one 
or more parameters are not supported the module report s 00h in both bytes of the configuration register for that 
parameter. 

Up to 24 different parameters can be monitored, each providing a real -time value as well as alarm and warning 
flags. 16 threshold value sets are provided, and each of the 24 parameters is associated by the module with one 
of the threshold value sets. The parameter configuration registers indicate which threshold set is to be used with 
each parameter. Note that this implies that multiple parameters may share the same threshold set (for example, if 
the same parameter is measured on multiple channels). 

To facilitate future functionality without major specification changes, the parameter configuration registers provide 
an enumerated value for the specific parameter to be monitored.  

In addition to parameter monitoring, this specification includes a read-only logical mapping indication feature which 
associates electrical channels with optical channels when that mapping is defined. 



6.7.2 Registers for Page 20h and 21h 
6.7.2.1 Overview 

(PDF p.68)

Table 6-36  Register overview for page 20h 
Byte Size Name Description P
C 
A
C 
A
O 
S
M 
128-139 12 Param Alarms Latched alarm/warning flags for monitored 
parameters (see 6.7.2.2) 
O O O O 
140-151 12 Param Masks Interrupt mask values for monitored parameters  
(see 6.7.2.3) 
O O O O 
152-199 48 Param Values Real-time values for monitored parameters  (see 
6.7.2.4) 
O O O O 
200-247 48 Param 
Configuration 
Parameter configuration registers (see 6.7.2.5) O O O O 
248-249 2 Lane mapping Lane mapping (see 6.7.2.6) O O O O 
250-255 6 Other 
configuration 
Error counter reset and other configurations (see 
6.7.2.7) 
O O O O 

(PDF p.68)

Table 6-37  Register overview for page 21h 
Byte Size Name Description PC AC AO SM 
128-255 128 Param 
Thresholds 
Parameter alarm and warning thresholds (page 
21h, see 6.7.2.8) 
O O O O 

6.7.2.2 Latched Alarm/Warning Flags for Monitored Parameters 
These 12 bytes cover the latched alarm and warning flags for the monitored parameters specified by the parameter 
configuration registers. Each parameter has 4 bits with the most -significant bit representing the alarm high error, 
followed by alarm low, warning high and warning low as with other alarm and warning flags.  Note that the threshold 
against which the real-time value is compared to generate these alarms and warnings is specified in the Parameter 
Configuration Registers. 

(PDF p.68)

Table 6-38  Latched Alarm/Warning Flags (Page 20h Bytes 128-139)  
Byte Bit Name Description PC AC AO SM 
128 7-4 L-Param1 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 1 
O O O O 
3-0 L-Param2 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 2 
O O O O 
129 7-4 L-Param3 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 3 
O O O O 
3-0 L-Param4 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 4 
O O O O 
130 7-4 L-Param5 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 5 
O O O O 
3-0 L-Param6 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 6 
O O O O 
131 7-4 L-Param7 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 7 
O O O O 
3-0 L-Param8 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 8 
O O O O 
132 7-4 L-Param9 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 9 
O O O O 
3-0 L-Param10 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 10 
O O O O 


Byte Bit Name Description PC AC AO SM 
133 7-4 L-Param11 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 11 
O O O O 
3-0 L-Param12 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 12 
O O O O 
134 7-4 L-Param13 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 13 
O O O O 
3-0 L-Param14 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 14 
O O O O 
135 7-4 L-Param15 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 15 
O O O O 
3-0 L-Param16 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 16 
O O O O 
136 7-4 L-Param17 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 17 
O O O O 
3-0 L-Param18 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 18 
O O O O 
137 7-4 L-Param19 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 19 
O O O O 
3-0 L-Param20 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 20 
O O O O 
138 7-4 L-Param21 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 21 
O O O O 
3-0 L-Param22 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 22 
O O O O 
139 7-4 L-Param23 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 23 
O O O O 
3-0 L-Param24 Alarm/Warning Latched alarm/warning flags for 
monitored parameter 24 
O O O O 


6.7.2.3 Mask Registers for Monitored Parameters 
These 12 bytes cover the interrupt masks for the latched alarm and warning flags. Each parameter has 4 bits with 
the most-significant bit representing the alarm high error, followed by low alarm, high warning and low warning as 
with other alarm and warning  parameters. When a particular bit is 0, then the corresponding flag generate s an 
interrupt. If the bit is 1 then an interrupt is not generated. As with the alarm and warning flags, for each parameter 
the highest bit number represents alarm high followed by alarm low, warning high and warning low masks. 

(PDF p.69)

Table 6-39  Interrupt Mask Registers (Page 20h Bytes 140-151) 
Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
140 7-4 M-Param1 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 1 
O O O O 
3-0 M-Param2 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 2 
O O O O 
141 7-4 M-Param3 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 3 
O O O O 
3-0 M-Param4 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 4 
O O O O 
142 7-4 M-Param5 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 5 
O O O O 


Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
3-0 M-Param6 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 6 
O O O O 
143 7-4 M-Param7 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 7 
O O O O 
3-0 M-Param8 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 8 
O O O O 
144 7-4 M-Param9 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 9 
O O O O 
3-0 M-Param10 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 10 
O O O O 
145 7-4 M-Param11 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 11 
O O O O 
3-0 M-Param12 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 12 
O O O O 
146 7-4 M-Param13 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 13 
O O O O 
3-0 M-Param14 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 14 
O O O O 
147 7-4 M-Param15 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 15 
O O O O 
3-0 M-Param16 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 16 
O O O O 
148 7-4 M-Param17 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 17 
O O O O 
3-0 M-Param18 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 18 
O O O O 
149 7-4 M-Param19 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 19 
O O O O 
3-0 M-Param20 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 20 
O O O O 
150 7-4 M-Param21 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 21 
O O O O 
3-0 M-Param22 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 22 
O O O O 
151 7-4 M-Param23 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 23 
O O O O 
3-0 M-Param24 Alarm/Warning Masking bits for alarm/warning flags for 
monitored parameter 24 
O O O O 


6.7.2.4 Real-Time Value of Monitored Parameters 
These 48 bytes contain the real-time value of the monitored parameters. They are to be interpreted as specified in 
the Parameter Configuration Registers. In addition, the module will compare these values to the corresponding 
thresholds indicated in the Parameter Configuration Registers to generate the appropriate alarms and/or warnings 
in the registers above. As with the rest of SFF-8636, these parameters are all stored with the most significant byte 
in the lower numbered address. 

(PDF p.71)

Table 6-40  Real-Time Value Registers (Page 20h Bytes 152-199) 
Byte Bit Name Description P
C 
A
C 
A
O 
S
M 
152 All Param 1 MSB Real-time value of parameter 1 (MSB) O O O O 
153 All Param 1 LSB Real-time value of parameter 1 (LSB) O O O O 
154 All Param 2 MSB Real-time value of parameter 2 (MSB) O O O O 
155 All Param 2 LSB Real-time value of parameter 2 (LSB) O O O O 
156 All Param 3 MSB Real-time value of parameter 3 (MSB) O O O O 
157 All Param 3 LSB Real-time value of parameter 3 (LSB) O O O O 
158 All Param 4 MSB Real-time value of parameter 4 (MSB) O O O O 
159 All Param 4 LSB Real-time value of parameter 4 (LSB) O O O O 
160 All Param 5 MSB Real-time value of parameter 5 (MSB) O O O O 
161 All Param 5 LSB Real-time value of parameter 5 (LSB) O O O O 
162 All Param 6 MSB Real-time value of parameter 6 (MSB) O O O O 
163 All Param 6 LSB Real-time value of parameter 6 (LSB) O O O O 
164 All Param 7 MSB Real-time value of parameter 7 (MSB) O O O O 
165 All Param 7 LSB Real-time value of parameter 7 (LSB) O O O O 
166 All Param 8 MSB Real-time value of parameter 8 (MSB) O O O O 
167 All Param 8 LSB Real-time value of parameter 8 (LSB) O O O O 
168 All Param 9 MSB Real-time value of parameter 9 (MSB) O O O O 
169 All Param 9 LSB Real-time value of parameter 9 (LSB) O O O O 
170 All Param 10 MSB Real-time value of parameter 10 (MSB) O O O O 
171 All Param 10 LSB Real-time value of parameter 10 (LSB) O O O O 
172 All Param 11 MSB Real-time value of parameter 11 (MSB) O O O O 
173 All Param 11 LSB Real-time value of parameter 11 (LSB) O O O O 
174 All Param 12 MSB Real-time value of parameter 12 (MSB) O O O O 
175 All Param 12 LSB Real-time value of parameter 12 (LSB) O O O O 
176 All Param 13 MSB Real-time value of parameter 13 (MSB) O O O O 
177 All Param 13 LSB Real-time value of parameter 13 (LSB) O O O O 
178 All Param 14 MSB Real-time value of parameter 14 (MSB) O O O O 
179 All Param 14 LSB Real-time value of parameter 14 (LSB) O O O O 
180 All Param 15 MSB Real-time value of parameter 15 (MSB) O O O O 
181 All Param 15 LSB Real-time value of parameter 15 (LSB) O O O O 
182 All Param 16 MSB Real-time value of parameter 16 (MSB) O O O O 
183 All Param 16 LSB Real-time value of parameter 16 (LSB) O O O O 
184 All Param 17 MSB Real-time value of parameter 17 (MSB) O O O O 
185 All Param 17 LSB Real-time value of parameter 17 (LSB) O O O O 
186 All Param 18 MSB Real-time value of parameter 18 (MSB) O O O O 
187 All Param 18 LSB Real-time value of parameter 18 (LSB) O O O O 
188 All Param 19 MSB Real-time value of parameter 19 (MSB) O O O O 
189 All Param 19 LSB Real-time value of parameter 19 (LSB) O O O O 
190 All Param 20 MSB Real-time value of parameter 20 (MSB) O O O O 
191 All Param 20 LSB Real-time value of parameter 20 (LSB) O O O O 
192 All Param 21 MSB Real-time value of parameter 21 (MSB) O O O O 
193 All Param 21 LSB Real-time value of parameter 21 (LSB) O O O O 
194 All Param 22 MSB Real-time value of parameter 22 (MSB) O O O O 
195 All Param 22 LSB Real-time value of parameter 22 (LSB) O O O O 
196 All Param 23 MSB Real-time value of parameter 23 (MSB) O O O O 
197 All Param 23 LSB Real-time value of parameter 23 (LSB) O O O O 
198 All Param 24 MSB Real-time value of parameter 24 (MSB) O O O O 
199 All Param 24 LSB Real-time value of parameter 24 (LSB) O O O O 



6.7.2.5 Parameter Configuration Registers 
These 48 bytes determine how the real-time value registers, alarms and warnings, masks and thresholds are to be 
interpreted by the host. For each of the 24 possible monitored parameters the monitoring point, parameter type 
and threshold location are provided by the module.  The parameter configuration is a 2-byte field which is described 
below. 

(PDF p.72)

Table 6-41  Parameter Configuration Registers (Page 20h Bytes 200-247) 
Byte Bit Name Description PC A
C 
A
O 
S
M 
200 All Config 1 MSB Configuration for parameter 1 (MSB) O O O O 
201 All Config 1 LSB Configuration for parameter 1 (LSB) O O O O 
202 All Config 2 MSB Configuration for parameter 2 (MSB) O O O O 
203 All Config 2 LSB Configuration for parameter 2 (LSB) O O O O 
204 All Config 3 MSB Configuration for parameter 3 (MSB) O O O O 
205 All Config 3 LSB Configuration for parameter 3 (LSB) O O O O 
206 All Config 4 MSB Configuration for parameter 4 (MSB) O O O O 
207 All Config 4 LSB Configuration for parameter 4 (LSB) O O O O 
208 All Config 5 MSB Configuration for parameter 5 (MSB) O O O O 
209 All Config 5 LSB Configuration for parameter 5 (LSB) O O O O 
210 All Config 6 MSB Configuration for parameter 6 (MSB) O O O O 
211 All Config 6 LSB Configuration for parameter 6 (LSB) O O O O 
212 All Config 7 MSB Configuration for parameter 7 (MSB) O O O O 
213 All Config 7 LSB Configuration for parameter 7 (LSB) O O O O 
214 All Config 8 MSB Configuration for parameter 8 (MSB) O O O O 
215 All Config 8 LSB Configuration for parameter 8 (LSB) O O O O 
216 All Config 9 MSB Configuration for parameter 9 (MSB) O O O O 
217 All Config 9 LSB Configuration for parameter 9 (LSB) O O O O 
218 All Config 10 MSB Configuration for parameter 10 (MSB) O O O O 
219 All Config 10 LSB Configuration for parameter 10 (LSB) O O O O 
220 All Config 11 MSB Configuration for parameter 11 (MSB) O O O O 
221 All Config 11 LSB Configuration for parameter 11 (LSB) O O O O 
222 All Config 12 MSB Configuration for parameter 12 (MSB) O O O O 
223 All Config 12 LSB Configuration for parameter 12 (LSB) O O O O 
224 All Config 13 MSB Configuration for parameter 13 (MSB) O O O O 
225 All Config 13 LSB Configuration for parameter 13 (LSB) O O O O 
226 All Config 14 MSB Configuration for parameter 14 (MSB) O O O O 
227 All Config 14 LSB Configuration for parameter 14 (LSB) O O O O 
228 All Config 15 MSB Configuration for parameter 15 (MSB) O O O O 
229 All Config 15 LSB Configuration for parameter 15 (LSB) O O O O 
230 All Config 16 MSB Configuration for parameter 16 (MSB) O O O O 
231 All Config 16 LSB Configuration for parameter 16 (LSB) O O O O 
232 All Config 17 MSB Configuration for parameter 17 (MSB) O O O O 
233 All Config 17 LSB Configuration for parameter 17 (LSB) O O O O 
234 All Config 18 MSB Configuration for parameter 18 (MSB) O O O O 
235 All Config 18 LSB Configuration for parameter 18 (LSB) O O O O 
236 All Config 19 MSB Configuration for parameter 19 (MSB) O O O O 
237 All Config 19 LSB Configuration for parameter 19 (LSB) O O O O 
238 All Config 20 MSB Configuration for parameter 20 (MSB) O O O O 
239 All Config 20 LSB Configuration for parameter 20 (LSB) O O O O 
240 All Config 21 MSB Configuration for parameter 21 (MSB) O O O O 


Byte Bit Name Description PC A
C 
A
O 
S
M 
241 All Config 21 LSB Configuration for parameter 21 (LSB) O O O O 
242 All Config 22 MSB Configuration for parameter 22 (MSB) O O O O 
243 All Config 22 LSB Configuration for parameter 22 (LSB) O O O O 
244 All Config 23 MSB Configuration for parameter 23 (MSB) O O O O 
245 All Config 23 LSB Configuration for parameter 23 (LSB) O O O O 
246 All Config 24 MSB Configuration for parameter 24 (MSB) O O O O 
247 All Config 24 LSB Configuration for parameter 24 (LSB) O O O O 




The two bytes of parameter are stored most significant byte-first with the following definition: 

(PDF p.74)

Table 6-42  Parameter Configuration Details 
Byte Bits Description 
MSB 7:4 Threshold ID. This num ber corresponds to which threshold set (1 -16) is to be used for this 
parameter. 
3 Reserved 
2 Parameter monitored at: 
0b = Global module 
1b = Channel-specific (see bits 1:0) 
1:0 Channel number, if the parameter is monitored channel-specific, per bit 2. 
LSB 7:0 Parameter type (see Table 6-43) 

The parameter type value is taken from the following table: 

(PDF p.74)

Table 6-43  Parameter Type Enumeration 
Value Description 
0 Parameter not supported. This value means that the module is not presenting any data on the 
corresponding real-time value, or latched flag registers. 
1 SNR, line ingress (see section 6.7.4.1) 
2 Residual ISI/Dispersion, line ingress (see section 6.7.4.2) 
3 PAM4 Level Transition Parameter, line ingress (see section 6.7.4.3) 
4 Pre-FEC BER, average, line ingress (see section 6.7.4.4) 
5 FER, average, line ingress (see section 6.7.4.4) 
6 TEC Current (see section 6.7.5.1) 
7 Laser Frequency (see section 6.7.5.2) 
8 Laser Temperature (see section 6.7.5.3) 
9 Pre-FEC BER, latched minimum value since last read, line ingress (see section 6.7.4.4) 
10 Pre-FEC BER, latched maximum value since last read, line ingress (see section 6.7.4.4) 
11 Pre-FEC BER, prior period, line ingress (see section 6.7.4.4) 
12 Pre-FEC BER, current, line ingress (see section 6.7.4.4) 
13 FER, latched minimum value since last read, line ingress (see section 6.7.4.4) 
14 FER, latched maximum value since last read, line ingress (see section 6.7.4.4) 
15 FER, prior period, line ingress (see section 6.7.4.4) 
16 FER, current, line ingress (see section 6.7.4.4) 
17-191 Reserved 
192-255 Vendor-specific 




6.7.2.6 Electrical/Optical Lane Mapping 
This read-only feature allows the host to retrieve the electrical to optical channel mapping. For a PAM4 encoding, 
the electrical channel can be either mapped to the MSB or the LSB of the optical channel. This parameter is read -
only. Each electrical channel has a 4-bit register in register 183 or 184 to define this mapping: 

(PDF p.75)

Table 6-44  Lane Mapping Registers (Table 20h Bytes 248-249) 
Byte Bit Name Description PC AC AO SM 
248 7-4 Mapping Lane 1 Line side mapping for electrical channel 1  (see 
Table 6-45) 
O O O O 
3-0 Mapping Lane 2 Line side mapping for electrical channel 2  (see 
Table 6-45) 
O O O O 
249 7-4 Mapping Lane 3 Line side mapping for electrical channel 3  (see 
Table 6-45) 
O O O O 
3-0 Mapping Lane 4 Line side mapping for electrical channel 4  (see 
Table 6-45) 
O O O O 

And the mapping is defined in Table 6-45. 

(PDF p.75)

Table 6-45  Lane Mapping Enumeration 
Value Description 
0 Not determined or not supported. This means that the data from the electrical lane could be 
spread amongst any optical lane and between LSB and MSB. This may be  the case for 
example, in FEC encoded data or Gray mapped data. Use this value also to mean that lane 
mapping is not supported. 
1 Optical Lane 1, LSB. This means that all of the data from the electrical lane appears on 
optical lane 1 in the LSB. 
2 Optical Lane 1, MSB. This means that all of the data from the electrical lane appears on 
optical lane 1 in the MSB. 
3 Optical Lane 2, LSB. This means that all of the data from the electrical lane appears on 
optical lane 2 in the LSB. 
4 Optical Lane 2, MSB. This means that all of the data from the electrical lane appears on 
optical lane 2 in the MSB. 
5 Optical Lane 1. This means that all of the data from the electrical lane appears on optical 
lane 1, but it might be LSB or MSB or spread between the two based on encoding. 
6 Optical Lane 2. This means that all of the data from the electrical lane appears on optical 
lane 2, but it might be LSB or MSB or spread between the two based on encoding. 
7-12 Reserved 
13-15 Vendor specific mapping 




6.7.2.7 Other Configuration Registers 
This section contains a single bit that enables the host to reset the module error counters so that a recent BER can 
be presented. Other bits and registers are reserved. 

(PDF p.76)

Table 6-46  Other Configuration Registers (Table 20h Bytes 250-255) 
Byte Bit Name Description PC AC AO SM 
250 7 Error Reset 1b = Reset error counters (clears back to zero 
automatically when the counters have been 
reset) 
O O O O 
6-0 Reserved Reserved - - - - 
251-
255 
All Reserved Reserved - - - - 




6.7.2.8 Threshold Registers 
This section contains the 16 threshold register sets against which the various parameters are to be compared to 
determine if an alarm or warning flag should be generated. Each threshold set has 4 2-Byte registers ordered most 
significant byte-first, and the registers are in the same order as other threshold registers in SFF -8636: alarm high 
threshold, alarm low threshold, warning high threshold, warning low threshold. The units of the threshold values 
are identified by the corresponding parameter value which is assigned to the threshold set. 

(PDF p.77)

Table 6-47  Threshold Registers (Page 21h Bytes 128-255) 

Byte Bit Name Description PC AC AO SM 
128-
135 
All Param Threshold Set 1 Threshold set 1, same order as other SFF -
8636 threshold sets 
O O O O 
136-
143 
All Param Threshold Set 2 Threshold set 2, same order as other SFF -
8636 threshold sets 
O O O O 
144-
151 
All Param Threshold Set 3 Threshold set 3, same order as other SFF -
8636 threshold sets 
O O O O 
152-
159 
All Param Threshold Set 4 Threshold set 4, same order as other SFF -
8636 threshold sets 
O O O O 
160-
167 
All Param Threshold Set 5 Threshold set 5, same order as other SFF -
8636 threshold sets 
O O O O 
168-
175 
All Param Threshold Set 6 Threshold set 6, same order as other SFF -
8636 threshold sets 
O O O O 
176-
183 
All Param Threshold Set 7 Threshold set 7, same order as other SFF -
8636 threshold sets 
O O O O 
184-
191 
All Param Threshold Set 8 Threshold set 8, same order as other SFF -
8636 threshold sets 
O O O O 
192-
199 
All Param Threshold Set 9 Threshold set 9, same order as other SFF -
8636 threshold sets 
O O O O 
200-
207 
All Param Threshold Set 10 Threshold set 10, same order as other SFF-
8636 threshold sets 
O O O O 
208-
215 
All Param Threshold Set 11 Threshold set 11, same order as other SFF-
8636 threshold sets 
O O O O 
216-
223 
All Param Threshold Set 12 Threshold set 12, same order as other SFF-
8636 threshold sets 
O O O O 
224-
231 
All Param Threshold Set 13 Threshold set 13, same order as other SFF-
8636 threshold sets 
O O O O 
232-
239 
All Param Threshold Set 14 Threshold set 14, same order as other SFF-
8636 threshold sets 
O O O O 
240-
247 
All Param Threshold Set 15 Threshold set 15, same order as other SFF-
8636 threshold sets 
O O O O 
248-
255 
All Param Threshold Set 16 Threshold set 16, same order as other SFF-
8636 threshold sets 
O O O O 
6.7.3 Diagrams for PAM4 Monitored Parameters 
Figure 6-1 below shows a general block diagram of the optical ingress path of a module showing the location where 
the SNR and level transition parameters are measured. 




Figure 6-1  Optical ingress path of Module 

Figure 6-2 is a view of the aggregate PAM4 data expressed as a histogram measured at a vertical slice in the center 
of the eye, showing the measurement method for SNR and level transition parameters.  


Figure 6-2  PAM4 vertical slice histogram 

The histogram x -axis is in bins and the y -axis is in number of bin hits. The number of bins and the hit count 
magnitude is vendor specific. The histogram is taken at the point in the time domain where data is converted from 
analog to digital. The PAM4 slicer determines the best points to split the data between values of 0, 1, 2 or 3. The 
peak is the bin with the largest number of counts between any two valleys (or below valley 1/above valley 3 for 
the first and last peaks). The valley location is deter mined by the slicer, and is the bin number where data below 
is considered to be i and data above is considered to be i+1. 









The calculations for the reported eye parameters are:  
SNR = 10* log10(min{SNR0, SNR1, SNR2 }) where SNRi= (µi+1- µi)/( σi+1+ σi), expressed in 1/256 dB 
units  
LTP = 10* log10(min{LTP0, LTP1, LTP2 }) where LTPi= (Pi+1+ Pi)/( 2Vi), expressed in 1/256 dB units  












For the vendor specified wavelength, the accuracy of the reported SNR and LTP parameters shall be better than 
+/-3 dB over specified temperature and voltage. 

6.7.4 Detailed Description of Additional Monitored Parameters for PAM4 
6.7.4.1 SNR 
This feature measures the electrical signal-to-noise ratio on the ingress optical channel, as defined in Figure 6-2. It 
is the minimum of the individual eye SNR values, where the SNRi for each of the three eyes is defined as the ratio 
of the difference of the mean voltage between neighboring levels divided by the sum of the standard deviations of 
the two neighboring levels. 

SNR is encoded as a 16 -bit unsigned integer in units of 1/256 dB. For example a value of 1380h is interpreted as 
an SNR of 19.5 dB. 
6.7.4.2 Residual ISI/Dispersion: 
Chromatic dispersion is monitored at TP3 and will report the same value as an external dispersion meter (e.g., an 
optical vector analyzer) would report. The units are 0.1 ps/nm. For the vendor specified wavelength and line width, 
the accuracy of the reported Residual ISI/Dispersion parameter shall be better than +/ -100 ps/nm over specified 
temperature and voltage. 

6.7.4.3 PAM Level Transition Parameter 
This feature measures the electrical level slicer noise, as defined in Figure 6-2. It is the minimum of the individual 
PAM level LTP values, where the LTP for each PAM level is defined as the average of the peak histogram intensity 
of neighboring PAM levels divided by the minimum histogram intensity between them. Both the SNR and LTP 
parameters measure signal-to-noise but the LTP parameter is more sensitive to a noise floor. 

PAM Level Transition Parameter is encoded as a 16-bit unsigned integer in units of 1/256 dB. For example a value 
of 3080h is interpreted as an LTP of 48.5 dB. It is possible that the minimum histogram intensity between PAM 
levels is actually zero in which case this parameter would be infinite. In this case the special value of FFFFh is used. 
If the parameter measures a value of greater than 255.996 dB but is not infinite, then FFFEh is used. 
6.7.4.4 Error Figures 
Frame error rate is reported in RS(544,514) FEC equivalent frames (see IEEE 802.3 Clause 91.5). If the actual FEC 
is not RS(544,514) then the measured frame error rate is converted. So for example, if the FEC frame size is 10% 
larger than the RS(544,514) FEC frame, then the reported frame error rate will be 10% higher than the measured 
frame error rate. This is done so as to be able to compare frame error rates regardless of the FEC encoding 
employed. 

Two different error figures may be supported: 

• RS(544,514) Frame Error Rate (FER): This parameter measures the uncorrected/errored RS(544,514) 
equivalent frames per second. 
• Pre-FEC Bit Error Ratio (BER): This is the total number of errored bits that were corrected by the FEC during 

Where, 

µi: level of ith peak, optionally averaged over neighboring bins 
σi: std dev of ith peak, optionally averaged over neighboring bins 
Pi: height of ith peak, optionally averaged over neighboring bins 
Vi: height of ith valley, optionally averaged over neighboring bins 


an interval divided by the total number of bits received in the interval. Note that different FEC schemes have 
different maximum pre-FEC BER requirements for a specific corrected BER maximum target. 

Both the BER and the FER are monitored using the following technique: 


Figure 6-3  Error rate accumulation intervals 

The module shall collect BER/FER data over a vendor -specific fine time slice, defined by the module (for example, 
1 ms). The host may read the data at a slower rate. 

The module calculates a BER/FER at each fine interval (light borders). The Host may have performance monitoring 
intervals (dark borders). Figure 6-3 shows a series (in time) of fine intervals punctuated by counter reset events 
that demark the host monitoring interval. If supported by the module, the host can read various calculated values. 
The selection of the which value(s) is/are available depends on the parameter type identifier (see Table 6-43). 

Current: 

If supported, the module shall keep a recent reading for the host to read at any time. This is referred to as the 
“instantaneous” value. For this value, a parameter type (See Table 6-43) of 12 for BER or 15 for FER is used. 

Average:  

If supported by the module, the average value shall be determined by using the counters reset function to program 
the averaging time interval. The module shall report a continuously averaged reading over the entire averaging 
interval. For this value, a parameter type of 4 for BER or 5 for FER is used. This value provides a glimpse as to how 
the current monitoring interval is performing. The module shall reset the counters for this purpose upon a write of 
1b to register 250, bit 7 on page 20h. 

Prior Period: 

This value is the total averaged in the last monitoring interval as defined by the two most recent counter reset 
events. This is provided to assure that an interval can be calculated regardless of how quickly the host is reading 
the data. 

If supported, the module shall allow the host to continue to read the BER/FER that was averaged between the last 
two counter reset events (i.e. between the two dark lines in Figure 6-3). For this value, a parameter type of 12 for 
BER and 16 for FER is used. The module shall reset the counters for this purpose upon a write of 1b to register 
250, bit 7 on page 20h. 

Latched Maximum/Maximum: 

This is the largest/smallest fine -interval calculation since the last time the host read the data. The host can then 



keep track of the maximum of these readings to report as an overall maximum/minimum within its performance 
monitoring interval. 

If supported, the module shall latch the lowest and highest (respectively) measurements it has calculated over any 
fine interval since the last time the host read each value. The module shall clear the corresponding latch when the 
host reads the value. These values are not cleared with the counters reset feature. For these values, a parameter 
type of 9 for BER minimum, 10 for BER maximum, 13 for FER minimum, and 15 for FER maximum is used.  

Note that the thresholds system is maintained for BER and FER, but the low thresholds should be 0, and the high 
threshold for FER should also be 0 unless other error correcting schemes are present. 

The error parameters are interpreted as an unsigned 16-bit floating point number with 5 bits for base-10 exponent, 
offset by -24, and 11 bits for mantissa. Thus the format is: 
𝑚 ∗ 10𝑠+𝑜 
Where m ranges from 0 to 2047 (11 bits), s ranges from 0 to 31 (5 bits) and o is fixed at -24. The smallest non-
zero number is m=1 and s=0 or 1*10^(-24). The largest number supported is m=2047 and s=31, or 2.047*10^10. 
Within the 2 bytes of the value (stored lowest byte first), m and s are encoded as follows: 

(PDF p.81)

Table 6-48  Encoding for BER/FER 
Byte Bits Description 
1 7:3 Exponent (s) 
1 2:0 Mantissa (m), bits 10:8 
2 7:0 Mantissa (m), bits 7:0 

6.7.5 Detailed Description of Additional Monitored Parameters for DWDM 
6.7.5.1 TC Current 
If supported, this parameter monitors the amount of current flowing to the TC of a cooled laser.  

It is a 16 -bit signed 2s complement value in increments of 0.1 mA. Thus the total range is from -3.2768 A to 
+3.2767 A. 

6.7.5.2 Laser Frequency 
If supported, this parameter monitors the difference (in frequency units) between the target center frequency and 
the actual current center frequency. It is a similar measurement to the Laser Temperature except expressed as a 
frequency difference instead of a temperature difference, and vendors may support one or the other measurement, 
or both. 

It is a 16 -bit signed 2s complement value in increments of 10 MHz. Thus the total range is from -327.68 GHz to 
327.67 GHz. 
6.7.5.3 Laser Temperature 
If supported, this parameter monitors the laser temperature difference between the target laser temperature for a 
cooled laser, and the actual current temperature. It is a similar measurement to the Frequency Error except 
expressed as a temperature difference instead of a frequency difference, and vendors may support one or the other 
measurement, or both. 

It is a 16-bit signed 2s complement value in increments of 1/256 °C. Thus the total range is from -128 °C to  
+128 °C. 





7 Address A2h Page 22h High Accuracy Timing 

Page 22h has been defined for parameters used for enhanced calibration for high accuracy timing. There are two 
formats depending on the format identifier at the start of the page. The two formats are  
• Calibration format for Optical Modules.  See Table 7-1 and section 7.4 
• Calibration format for Loopback Modules. See Table 7-2 and section 7.5 

This specification describes a multi -lane memory map where Lane N is defined to be within (1 -8).  In SFF -8636  
Lanes 1-4 (N=4) applies. 

Format ID (Bytes 128-129) 

Format ID determines if page 22h contains a valid entry. One of the following valid values determines the format 
of the definition.  The following formats are defined: 

• CA1Bh => 'CALB' Calibration format for Optical Modules (see section 7.4) 
• 100Bh => 'LOOB' Calibration format for Loopback Modules (see section 7.5) 

CC_CALIB (Byte 255) 

This check code is a one-byte code that can be used to verify that the 127 bytes of calibration configuration data 
are correct. It uses byte 128 to 254 inclusive to calculate the check codes. This method is the same as the CC_* 
check code computation in other tables in the document. 


In the discovery of this page the host shall read and validate the format ID bytes 128 -129 as well as a checksum 
CC_CALIB to be as expected before the data of this page is used. 



Table 7-1  Register Summary Page 22h – Calibration format for Optical Modules 
A2h Size 
Bytes 
Name Description 
128-129 2 Format ID CA1Bh – Indicates page 22h has the calibration format for 
Optical Modules 
130-149 20 Common Header Common Header, see section 7.3 
150 1 Nb_Lanes Number of lanes for which delays are specified in the 

Source tables: 8-4 (overview) through 8-26.

Copper cable attenuation note: pre-5.4 (footnote in Table 8-29 area) this field group at 00h:204-209 was passive-copper-only; as of Rev 5.4 it also covers linear active copper cables ("Up to CMIS 5.2 this field was for passive copper cables only").

Source tables: 8-27 through 8-42.

Source tables: 8-43 through 8-62.

Source tables: 8-63 through 8-65.

Page 0Ch — Module Management (printed p.218-219, Table 8-69 to 8-73) — entirely new in 5.4

• 128-159: MapOfSupportedPages — 32-byte bitmask, systematic advertisement of every supported Page (bit k of byte 128+n ⇒ Page index n·8+k)
• 160-163: Named Feature Advertisements — ConsolidatedPmFeature (160-161), LoadManagementFeature (162-163), each a 2-byte FeatureSupport(CmisRevision)/OptionsCompliance/RequirementsCompliance structure
• 192-195: Named Feature Details — NaSupportDetails(192)/NaSupportOptions(193) for Consolidated PM; FwSupportDetails(194)/FwSupportOptions(195) for FW Load Management
• 196-255: Reserved

Page 0Dh — Firmware Management (printed p.219-220, Table 8-74 to 8-76) — new in 5.4

• 128: CapabilitiesRegister (CdbDownloadSupported, FixedLoadProvidesService, FixedBankSupported, BankB/ASupported)
• 136: LoadsStatusRegister (ValidityStatus/AdministrativeStatus/OperationalStatus for Bank A and B)
• 148-183: VersionLoadA, 184-219: VersionLoadB, 220-255: VersionFixedLoad (each: MajorVersion/MinorVersion/BuildNumber/ASCII[32] Description)

Page 1Ch — Normalized Application Descriptors, banked (printed p.298, Table 8-172 to 8-174) — new in 5.4

• 128-247: 15× 8-byte NAD structures (HostInterfaceID, MediaInterfaceID, lane counts, lane assignment options, NetworkPathIndicator, HostInterfaceGID/MediaInterfaceGID) — enables up to 255 banks × 15 = 3825 Applications addressed by 12-bit Application Number
• 248-255: Reserved

Page 1Dh — Host Lane Switching, banked (printed p.299-300, Table 8-175/8-176) — new in 5.4

• 128: MaxRedirectionCommitDuration (advertisement)
• 136-143: RedirectionOfLane1-8 (provisioning, RW)
• 152: EnableHostLaneRedirection
• 160: CommitRedirection (WO/SC trigger)
• 168-175: RedirectionCommitResult1-8 (0=none,1=success,2=in progress,3-6=various rejection reasons)
• 184-191: RedirectStatusOfLane1-8 (committed status)

These exist in the old CMIS5.3 Lookup_Table file as separate sheets but were out of scope for this extraction pass (too large / catalog-only, low differential value vs. the old file's own content which is mostly stable code-point lists inherited from SFF-8024, not CMIS-chapter-8 register definitions):

• Table 8-1 List of CMIS 128-Byte Pages and Banks (p.161) — full page map, useful as a table-of-contents cross-check
• Host Electrical Interface IDs, MMF/SMF/Copper/AOC/BaseT media interface ID tables — these live in SFF-8024, not in the CMIS spec itself; old file's corresponding sheets should be re-sourced from SFF-8024 Rev 4.14 (not yet downloaded in this session), not from CMIS54.pdf
• Page 10h/11h (Staged/Active Control Set lane configuration, Tables 8-77 to 8-107) — large lane-control register blocks (banked), old file had 131×25 sheets for these; not re-extracted here — would need a dedicated pass
• Page 04h (tunable laser), Page 12h/13h/14h (diagnostics/pattern gen), Page 16h-19h (Network Path), Page 20h-2Fh VDM pages 8-178/8-181 to 8-186 (VDM descriptors/thresholds/flags — only the Type table 8-180 was pulled), Page 60h-62h (acquisition counters) — not transcribed

• 00h:8.3 AbnormalFwIndicationFlag, 00h:31.3 AbnormalFwIndicationMask
• 00h:61.7-4 SFF8024HeatsinkType
• 01h:142.1-0 = 11b escape code for >32 lanes (was reserved)
• 01h:171 DefaultInputPolarityTx, 01h:172 DefaultOutputPolarityRx (moved/formalized)
• 01h:173-174 Supported Pages and Banks (additional): PageChSupported, PageDhSupported, ExtraLaneBanksSupported
• 01h:175 NADBanksSupported widened to U8 (was 4-bit)
• 01h:252.7 HostLaneSwitchingSupported, 01h:252.6 LinkTrainingSupported (CMIS-LT), 01h:252.5 MediaLaneSwitchingSupported
• New Pages: 0Ch (Module Management / supported-pages bitmask + named features), 1Ch (banked NAD), 1Dh (banked Host Lane Switching)
• VDM Type IDs 27-34 (SEWmax stats), 77-83 (CPO power rails), 84 (ELS input power)
• New CDB commands: 0044h/0045h (security/externally-defined features query), 0050h/0051h (app attributes / interface ID description), 0220h (RMON stats), 0230h-0233h (FEC SEW histogram/max stats), 0400h-0406h (secure device authentication)